ON THE VERIFICATION FRONT
Continuing its drive to make hardware-assisted verification available to the masses, EVE will launch ZeBu-Server, a scalable emulation system capable of handling up to 1 billion ASIC gates. Priced at less than a penny per gate for large configurations, ZeBu-Server offers a high level of automation, short compile time, multi-user capabilities, and fast execution speeds.
ZeBu-Server suits all SoC verification needs across the entire development cycle, from hardware verification and hardware/ software integration to embedded software validation. It can be used as a multi-user, multi-mode accelerator/emulator with a typical performance of 10 MHz on a 40 million-gate design. Included with the hardware is a compiler with multicore capability to break the linearity of the compile time on large designs.
ZeBu-Server offers automated, fast, and incremental compilation from SystemVerilog, Verilog, and VHDL RTL code. As an interactive hardware/software debugging tool, ZeBu-Server includes complete RTL signal dumping and support for SystemVerilog Assertions. ZeBu-Server is shipping now and is priced from $150,000.
Formal verification is another technology that’s growing in popularity, especially as the number of functional modes in portable devices rises. At DAC, Jasper Design Automation is announcing a technology it calls QuietTrace, which brings advanced visualization technology for RTL development. It also delivers enhanced behavioral analysis, with multiple RTL revision comparison supporting incremental design.
Jasper will also demonstrate its ProofGrid technology, which is available in its forthcoming JasperCore product as well as in the JasperGold verification environment. ProofGrid technology efficiently delivers formal proof power for multiple proofs, multiple tasks, multiple users, multiple applications, and multiple computers, even across multiple business units, Jasper says. It also represents core engine enhancements for faster proofs and lower memory consumption, leading to higher proof capacity.
In the functional verification arena, Real Intent will be at DAC to showcase its latest technology in its Ascent, Meridian, and PureTime family of products. Ascent, an early functional verification (EFV) tool, has been upgraded with enhanced static linting capabilities and additional path-based formal analysis capabilities, such as X-propagation verification to ensure safe X handling in the design utilizing automatic formal techniques.
Meridian CDC, which performs clock-domain-crossings (CDC) verification, now can perform hierarchical analysis and verify designs with free-running clocks. PureTime, a timing-exception verification tool, now offers enhanced design-constraint checking capabilities. Together with timing exception verification, designers can improve the quality of design constraints.
OneSpin Solutions will demonstrate a new root cause analysis framework that eases and speeds property and design debugging, increasing formal assertion-based verification (ABV) productivity. OneSpin’s formal ABV technology helps design, verification, and integration engineers to significantly accelerate a wide range of RTL verification tasks. OneSpin will present two ongoing inbooth tutorials, one designed for formal ABV newcomers to get started, and one for experienced users to take formal ABV to the next productivity and quality level.
GateRocket will show a new version of its RocketDrive FPGA verification and debug platform for Altera’s Stratix IV line, along with updated RocketVision software featuring dynamic block selection, on-the-fly scope selection, and full mixed Verilog/ VHDL support. Both are now available.
Analog/mixed-signal designers still rely on Spice, with many turning to fast-Spice variants. Berkeley Design Automation will demo the latest release of its Analog FastSpice (AFS) unified circuit verification platform. In addition to the speed boost that fast-Spice users are accustomed to, the 2009_05 release of AFS includes upgraded matrix solvers that deliver efficient convergence and fast transient analysis for pre-layout and post-layout circuits with up to 10 million elements. Also, a multicore capability delivers a further performance gain.
If you’re a Spice user, you probably will want to check out Altos Design Automation’s Liberate MX, an ultra-fast, generalpurpose library characterizer for memories and custom macro blocks. The new tool generates instance-specific library models in Liberty format including advanced current source models for timing and noise (CCS and ECSM).
Unlike traditional block characterization approaches that perform partitioning based on circuit topology, Liberate MX’s use of dynamic partitioning lets it account for effects common at advanced process nodes such as interconnect coupling and transistor stress. Liberate MX does not rely on circuit pattern matching and hence can be used for a very wide range of circuit types from complex lower-power SRAMs with power gating to custom blocks such as serializers-deserializers (SERDES).
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