[Design Application]
Protect Your High-Speed Circuits From ESD Transients
Fast interfaces like USB 2.0 and IEEE-1394 call for voltage-variable ESD suppressors with very low capacitance and minimal off-state current leakage.
Electrostatic discharge (ESD) frequently occurs in nature, and in the electronics equipment environment, with very damaging results. Indeed, it's responsible for more than 25% of the semiconductor chip damage happening during wafer fab, through various stages of circuit assembly, and on the completed and in-use electronics equipment.
Typically, the discharge stems from a human body part (finger) being in close proximity to electrically charged dissimilar materials, and then subsequently to conductive contact points attached to electronic devices. At best, this causes damaged ICs and warranty claims against the manufacturers of the end-user devices.
This problem is so serious that the European Union (EU) has defined specific standards of ESD suppression for any product sold in that economic zone. Now designers must provide effective ESD protection for today's ever-more-sensitive semiconductors.
Unfortunately, this task often follows an afterthought design principle: first build the circuit without additional overvoltage transient suppression, relying on the on-board IC protection. If tests indicate sensitivity during the prototype phase, then add the protection devices. If this approach is taken with today's lower operating voltages, increasing frequencies, and lower noise requirements, the entire design must be optimized and integrated. Adding the protection at the end can be more expensive, or impractical due to time constraints.
Generally, ESD events are described by three primary ESD algorithms based on the type of charge process and severity of transient surge: the human-body model (HBM), the charged-device model (CDM), and the machine model (MM). These models define the types of transient threats so engineers can define specific semiconductor chip-overvoltage transient-level sensitivities, plus chip and assembled product-test procedures. Using these models, circuit designers can test the ESD protection effectiveness of a chip and product uniformly—and quantitatively compare alternative solutions.
The direct transfer of charge through a series resistor, such as a human finger, is the most common source of ESD damage. Thus, the pre-eminent ESD model is the HBM. This is represented by the discharge of a 100-pF capacitor through a 1500-Ω resistor into the device under test (DUT). The commercial version of this standard has been the mil-spec (military specification) 883 Method 3015 (Fig. 1a).
The most prevalent HBM variant is the International Electrotechnical Commission (IEC) 1000-4-2 standard defined by a 150-pF discharge through a 330-Ω resistance (Fig. 1b). This is the recognized international test required by the EU for any product sold in that region.
However, significant transient-voltage-threat and energy-level differences exist between the two models. So designers tailor the test process to that expected for their specific application. For example, IEC 1000-4-2 has a much faster voltage-pulse rise time, more pulses applied, and higher peak current (see the table).
Recently, circuit designers have been adding protection via a number of transient-voltage-suppressor (TVS) devices. Some examples include solid-state devices (diodes), metal-oxide varistors (MOVs), thyristors, other voltage-variable materials (new polymer devices), gas tubes, and simple spark gaps.
Such devices are positioned between the incoming surge and ground. They rapidly change their resistance to a low state when the incoming voltage surge reaches a level that causes them to "turn on" or conduct. Ideally, the incoming threat is partially reflected back, while the balance is partially shunted to ground through the conducting TVS device. So, a smaller portion of the threat reaches the sensitive IC in the circuit.
But ESD suppression devices all have advantages and disadvantages. With the advent of new high-speed circuits, some disadvantages have been magnified. For instance, the TVS must respond very quickly to the incoming surge. The threat voltage reaches its 8-kV (or higher) peak in 0.7 ns. The trigger or clamping voltage of the TVS device (in parallel with the input line) must be low enough to be an effective voltage divider.
Some devices shield the circuit but wear out after just a few pulses—and/or fail in a low resistance (shorted) condition, leaving the circuit with a high current drain to ground. This is, of course, deadly for battery-operated devices.
Each device has its own anomalies. Gas tubes carry high currents, yet are very slow to respond. They also wear out and don't recover. MOVs have a relatively slow turn-on response for high-speed circuits. Silicon diodes have a very fast trigger response and low turn-on voltages. But like MOVs and the other devices, their capacitance is relatively high, which degrades high-speed signals.
The higher the frequency, the worse the effect of the capacitance. New voltage-variable ESD devices are the only products currently capable of offering extremely low capacitance and very low off-state current leakage. Plus, they're self restoring after many pulses.
Reprints
