Electronic Design

  
Reprints     Printer-Friendly    Email this Article    RSS        Font Size     What's This?


[Product Innovation]
Scalable, Reconfigurable Processor Adjusts Logic For Top Performance
An array of processing tiles, coupled with a reporgrammable fabric, can adjust its on-chip resources in a single cycle to optimize itself for the task at hand.

Dave Bursky  |   ED Online ID #3464  |   May 15, 2000


A single CS2112 chip can implement 50 channels of cdma2000 chip-rate processing, which is about twice the rate of other application-specific chips. Moving results onto or off the chip is possible with up to 160 programmable-I/O pads divided into banks of 40 I/Os each. Every bank delivers data at transfer rates of up to 0.5 Gbytes/s. That speed allows high-performance data streaming for signal-processing and protocol-processing applications.

The CS2112 holds four I/O port banks, which provides a total possible bandwidth of 2 Gbytes/s. The programmable lines can be configured to provide interface and handshake signals for SRAMs, peripheral functions like analog-to-digital and digital-to-analog converters, FPGAs, and other support circuits.

The RISC processor core, associated PCI controller, memory controller, and DMA subsystem provide the intelligence to manage the chip's overhead operations. The core coordinates with the host to ensure that data and algorithms flow smoothly.

The ARC RISC core is a 32-bit processor. When clocked at 125 MHz, it delivers about 120 MIPS. The processor has a four-stage pipeline, 64 general-purpose 32-bit registers, a 32-bit address space, a 4-kbyte instruction cache, and a 4-kbyte data memory. Also, to ease the system debug phase, Chameleon's designers implanted a full JTAG interface that works with the debug tools.

The PCI controller offers a complete interface for the chip to tie directly to a 32-bit PCI backplane. Functioning at bus speeds of up to 66 MHz, it handles both master and slave modes. As part of the control logic resources, a 64-bit memory controller was integrated to control the external memory. It handles synchronous SRAM and SDRAM, in addition to flash memories. It permits automatic transparent SDRAM refresh and supports up to four banks of SDRAM. Burst sizes up to 8 kbytes are possible. Both parity and 8-bit ECC support are included.

A separate configuration controller manages the data flow into the two configuration planes. The controller is an optimized DMA controller that transfers configuration data from off-chip memory, through the 64-bit memory controller, and into the background configuration plane.

Developing configuration patterns for the chips is straightforward with the C~Side development environment. C source code can be written to run on the ARC processor. At the same time, library circuit elements and Verilog HDL source code can be assembled and then synthesized to craft the compute functions. After the logic is synthesized, placed, and routed, the configuration bitstream is linked with the ARC object code. The outcome is an executable file that will run on the reconfigurable communications processor (Fig. 3).

ChipSim is an integral part of the tool suite. It's a complete simulator, and can be used to model the entire RCP. On the front end, the popular GNU debugger is available. ChipSim guarantees 100% visibility into all memories and registers throughout the RCP, both in the fabric and in the ARC core. A development board speeds up the application integration phase and permits designers to test the applications at full speed. By using the PCI bus or the JTAG port, data can be transferred. All memories and registers can remain visible to the debug tools, just as with the simulator.

Price & Availability
Samples of the 12-tile CS2112 reconfigurable processor will be available in the third quarter of this year. In 100-unit sample quantities, the processor sells for $295 apiece, but high-volume pricing will decrease to the equivalent of less than $1 for a cdma2000 chip-rate processing channel by the middle of 2001. The C~Side development tools also will ship in the third quarter. The complete software tool suite, which runs on the Sun Solaris platform, sells for $25,000. The hardware development board and related driver software sells for $5000.

Chameleon Systems Inc., 1195 W. Fremont Ave., Sunnyvale, CA 94087; Bruce Kleinman, (408) 730-3300, www.cmln.com.


<-- prev. page     1 2 [3]     next page -->

Reprints   Printer-Friendly  Email this Article  RSS    Font Size   What's This?


  • Network-On-Chip Tools Arrive for The Masses
  • Tackling System Design Challenges Through Early Verification
  • ESL Tools Take Center Stage As Designers Move Up
  • Parasitic Extraction Tool Targets Next-Generation Custom ICs
  • Synopsys Jumps Into ESL-Synthesis Pool
  • Verify Control Systems Before Committing To Hardware
  • You're Using How Many FPGAs?
  • Tool Up For The FPGA Blitz
    1) Build A Smart Battery Charger Using A Single-Transistor Circuit
    (181 views today)
    2) Hot Hands For Some Cool Rock: Motion Sensing Meets Audio Engineering
    (167 views today)
    3) What's All This Transimpedance Amplifier Stuff, Anyhow? (Part 1)
    (72 views today)
    4) GPS-Derived Grandmaster Clock Delivers Ultra-Precise Time And Frequency Sync
    (70 views today)
    5) Downconverting Mixers Lower Power Consumption While Improving Performance
    (55 views today)
    ALL TOP 20



    POST YOUR COMMENTS HERE
    Name:

    Email:
    Your Comments:

    Enter the text from the image below


    Please refresh the page if you have trouble reading this text.

    Search Electronic Design
         
      
     
    Web Seminar
    Sponsored By:
    Title: Read Pacing: A Performance Enhancing Feature of PCI Express Gen 2 Switch Devices
    Speakers: 
    Date: 07/01/08
    Register: 

    Electronic Design Europe Electronic Design China EEPN Power Electronics Auto Electronics Microwaves & RF
    Mobile Dev & Design Schematics Find Power Products Military Electronics EE Events Related Resources