[Technology Report]
Advanced VLIW Architectures Unleash Raw DSP Horsepower
A new wave of DSPs boasts a tenfold improvement in signal processing while slashing power to a new low.
All of these improvements mean that applications that were unthinkable before are now possible. For instance, TI says that the core can implement up to 32 full-rate DSL channels on a single chip or hundreds of voice-over-IP (VoIP) lines. Additionally, for wireless systems, the core could form the basis of an ASIC or standard solution that could handle up to 64 voice/data channels or high-quality video transmission to personal terminal devices. In the industrial arena, the raw horsepower and high throughput could be applied to provide a fivefold improvement in 3D imaging or a tenfold enhancement in machine vision, TI says. With consumer applications, the firm believes that the core could be applied to provide MPEG-2 audio and video decoding functions, as well as picture formatting in an HDTV receiver.
Although standard solutions may come later in the year, Nokia Mobile Phones is already developing custom devices based on the C55x core for handset applications. The initial versions of these cores will be implemented in a 0.15-µm CMOS process, with plans to quickly migrate to 0.12 µm. The first derivatives of the C55x are expected to be released this spring. Also, the early C55x designs will operate at 1.5 and 0.9 V.
With migration toward finer geometries, the power-supply requirements will be shrunk to 0.75 to 0.7 V. Slated for sampling sometime this summer, the C64x will initially run at 700 to 800 MHz. Specific ASIC solutions derived from this core are expected to be released in the second half of this year.
Both of the new cores are software-compatible with previous generations and supported by the eXpressDSP, TI's integrated development environment (IDE) launched last fall. TI has even refurbished the IDE's major ingredients, such as the Code Composer Studio and the real-time DSP/BIOS kernel. Code Composer Studio 1.2 comes with visual linking and profile-based compilation capabilities, letting users graphically optimize code size and performance tradeoffs.
The extended DSP/BIOS II kernel features a multitasking scheduler, I/O control, real-time analysis, and real-time data exchange (RTDX), giving DSP developers flexibility, scalability, and ease of implementation. "Integrated with the Code Composer Studio 1.2, the BIOS II kernel allows designers to abstract via an API," says DSP/BIOS II product manager Dan Davis. "Optimized for the C64x and C55x architectures, the DSP/BIOS II kernel requires minimal memory."
"In essence, the eXpressDSP is a completely uniform development environment for both C5000 and C6000 DSP platforms," notes Rich Scales, product manager for TI's Compiler Technology. The new extensions include profile-based compilation (PBC) for the C6000 platform, along with a Visual Linker to the Code Composer for the C5000 DSPs. Presently unique to C6000 DSPs, the PBC permits users to graphically select the optimum combination of code size and speed for the intended application. Consequently, it automates the evaluation of multiple options for each software function to provide optimum performance for a given code size, or the best code size for a given performance level.
Support for C++ is another addition to the C6000 DSP C compiler. Though C++ doesn't improve efficiency, it adds a higher level of abstraction. "We view it as a front-end piece. The compilation efficiency will depend on how good the C compiler is," Scales says. As a result, TI has focused on improving the out-of-the-box C code performance as well as optimizing it for a specific architecture.
Plans are under way to extend C++ support to the C5000 platform in the near future. Meanwhile, users of C5000 DSPs can enjoy the benefits of the Visual Linker component of Code Composer Studio 1.2. This linker is a piece of the tool chain that places the code in memory. Each DSP has its own memory map that visualizes and simplifies system memory allocation, enabling the user to see where the code is residing and how fast it is performing.
TI isn't alone in promoting compiler-friendly architectures and C++ for DSP programming. More and more DSP designers are leaning toward C. Nowadays, every small and large DSP provider is coming into the market battlefield armed with an efficient C compiler. It has become a critical weapon in their development arsenals. Lately, they've been adding an objected-oriented high-level programming language to it, too.
Analog Devices Inc. is another major contender that sees C++ as a natural progression to aggressively shorten time-to-market. "Our implementation of C++ takes this a step further by providing easier access to specialized features in DSP architectures," explains Geoff Millard, compiler manager for DSP tools at ADI. "As memory sizes and program complexity increase, DSP software developers are beginning to run into issues that non-DSP C programmers ran into several years ago—most notably, a lack of data encapsulation."
Millard adds that "because C++ is an extension to C, C++ has become the de facto programming language for many software projects in non-DSP applications. ADI expects DSP applications will follow suit. This is a vehicle for portable-language enhancement, and it facilitates code portability and reusability. There is no inherent C++ penalty, as it offers the same speed and code compactness of C."
Internal tests indicate that the compiled code for an innermost loop of an FFT performs equally well for either source form (see the code listing). This object-oriented capability is fully integrated within ADI's VisualDSP development environment, and it complies with the embedded C++ standard. It also has been tweaked to support both fixed- and floating-point DSP architectures offered by ADI. These include SHARC, TigerSHARC, and ADSP-218x/219x families. While the beta version of the C++ compiler has been unveiled for SHARC and TigerSHARC members initially, the fixed-point series ADSP218x/219x is slated to get C++ support in the fourth quarter of this year.
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