[Technology Report]
Advanced VLIW Architectures Unleash Raw DSP Horsepower
A new wave of DSPs boasts a tenfold improvement in signal processing while slashing power to a new low.
"Prior to this tool, DSP programmers experienced difficulty analyzing the behavior of their assembly code," notes Anne Mascarin, DSP market segment manager at The MathWorks. "Consequently, it was difficult for engineers to determine whether the assembly code was performing the functions for which it was designed."
To facilitate FPGA adoption in mainstream DSP applications, The MathWorks has entered a strategic alliance with Xilinx Inc. Its mission is to give designers a way to develop high-performance DSP systems on FPGAs using The MathWorks' system design and verification tools. In reality, the two partners have been working quietly for two years to create a solution that automatically translates system-level design into FPGA implementation. "It will open up the usage of FPGAs to the DSP designer community," says Per Holmberg, product marketing manager at Xilinx.
"Today, the price gap between high-density FPGAs and ASICs or single-chip DSPs is negligible," Holmberg adds. "They have evolved to become production parts. And, they can significantly reduce development time. This tool will enable designers to build and verify an entire DSP system and then automatically generate an HDL representation compatible with Xilinx FPGA implementation (Fig. 3). It will automatically map the DSP design to the Xilinx LogicCORE building blocks for optimal implementation and lowest silicon cost."
Traditionally, DSP developers have opted between an ASIC/ASSP and a programmable DSP processor. An FPGA combines the performance and system integration of ASICs/ASSPs with the reprogrammability and time-to-market benefits of processors. The Xilinx system generator for The MathWorks' Simulink interface is expected to be released in the third quarter of this year.
Unlike traditionally bus-oriented architectures, BOPS Inc. has taken the cluster-switch approach. With three levels of parallelism involving indirect VLIW, SIMD, and MIMD on top of a cluster switch, BOPS has generated three sets of a synthesizable Verilog DSP core for system-on-a-chip (SoC) solutions. Adopting a licensing strategy, the design house has crafted single-, dual-, and quad-processor versions for array processing in DSP applications.
BOPS provides a complete tool chain that includes a GNU C compiler. This tool allows direct conversion of MATLAB models into BOPS-optimized assembly code without going through C. For those who prefer C, BOPS also provides a parallelizing C compiler that exercises parallelism at three different levels for generating compact code. Vivsis, a subsidiary of Mitsubishi, and SiByte, a MIPS-architecture startup, license BOPS' proprietary cores. In fact, SiByte is developing SoCs for Internet appliances. Concurrently, BOPS is looking to improve the fundamental core with the addition of the PCI bus, a 64-bit DRAM bus, and a 32-bit MIPS interface.
Others following the licensing path for growth include LSI Logic, Infineon, Massana, and 3DSP. Philips Semiconductors and Hitachi Semiconductor are eying emerging sockets in this fray as well. To strengthen its position in high-growth wireless infrastructure and networking applications, LSI Logic has expanded its CoreWare ASIC library with ZSP's 400-MIPS superscalar DSP engine. For its ZSP core, the company has garnered support from Broadcom Corp., Brecis Communications, and TollBridge Technologies—a developer of IP-based multiline voice solutions. Brecis intends to employ the ZSP400 core in VoIP solutions.
To further add vitality to the ZSP400 core, LSI has added an addressing mode register for fast Fourier transforms, eight more shadow registers for context switching and low-latency interrupts, and two extra loop registers for minimizing the code. Plus, it has increased the memory size to address large programs as well as split the memory into data and program banks. LSI's software tools manager Prasad Kalluri adds that the associated compiler has been streamlined with better machine description for 10% faster code generation, since tools are important. A new cycle-accurate simulator replaces the older model.
Though not as powerful as other VLIW-based cores, Infineon continues to refine the configurable long-instruction-word CARMEL core with additional bells and whistles to lure system-level DSP designers. The latest CARMEL model, the DSP20xx, comes with a PowerPlug accelerator that lets developers configure the instruction set and modify the core. Subsequently, the new accelerator can implement computation-intensive features like multiple data rates and complex modulation schemes without compromising power dissipation and system costs. Designed to operate at frequencies up to 300 MHz, the latest CARMEL is expected to be available in the fourth quarter.
Traditionally, VoIP implementations and cable-modem applications have demanded separate DSP and RISC microcontrollers. DSPs efficiently perform telephony middleware tasks, and RISCs execute control tasks adequately. In turn, Hitachi Semiconductor is considering packing multiple 133-MIPS SH3-DSP cores on a single die.
"A DSP has a lot of deterministic requirements," says Peter Carbone, manager for Hitachi's microprocessors and microcontrollers. "There is uncertainty with a RISC+ DSP hybrid structure like the SH3-DSP. By using multiple cores, the device can be architected to do more DSP tasks on one, and put control tasks on another." Hitachi is evaluating such an approach with two cores on a single chip using a 0.18-µm CMOS process. Standard multiple core-based devices are planned for release in 2001, according to Hitachi.
To improve the performance of the 133-MIPS SH3-DSP, its developers are optimizing the chip's instructions and enhancing its speed. Simultaneously, a better C compiler is in the works that will generate assembly code for the SH3-DSP. In addition to speeding up development of VoIP, the company has ported a media-gateway control protocol to the SH3-DSP, as well as readied a VoIP reference design with telephony middleware.
Suppliers Of DSP Chips And Cores
Analog Devices Inc. (781) 329-4700 www.analog.com
BOPS Inc. (650) 330-8407 www.bops.com
Hitachi Semiconductor (America) Inc. (800) 285-1601 www.hitachi.com
Infineon Technologies Inc. (408) 501-6880 www.infineon.com
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