[Product Innovation]
Integrated USB 2.0 Chip Extends Its Reach To High-Speed Peripherals
This chip promises designers time-to-market and other advantages when implementing the new 480-Mbit/s standard.
The Cypress Smart USB 2.0 SIE, like the company's previous FX part, implements most of the USB 2.0 protocol. Because this is the case, the designer doesn't have to worry about things like all three stages of a control transaction, nor does the microprocessor need to become involved. That is all handled by the Smart SIE.
Cypress says it's in a unique position. When a customer orders the company's development board and plugs it into a PC, the board works without having to write any code. This is due to the Smart SIE. Obviously, the board won't be tuned to the user's application, but there's no frustration involved in getting the part to work. USB transfers take place immediately.
One other job handled by the Smart SIE is the Cypress firmware downloading. The firmware is in RAM in the FX2, so it can be downloaded using USB through the SIE. The SIE can do the downloading while the processor is in reset. Because the USB 2.0 specification is brand new, problems are certain to be encountered. Downloading provides the designer an easy way to update the part if the specification changes. The company considers this to be a major advantage because it decreases risk and uncertainty, and it increases time-to-market advantages.
A key point about the endpoint FIFO is that it's implemented as a dual-port RAM. USB is a packet protocol, which sends a whole packet of data at once. In USB 2.0, those packets are 512 bytes. If a classic FIFO is used and a bad CRC occurs, all the data has to be flushed out because it's bad data. By implementing the FIFO as a RAM, it becomes more like a packet FIFO. The whole packet can be loaded into the dual-port memory. If the CRC is fine, that packet can be swapped from the USB domain to the I/O domain. To the outside world, it still looks like a FIFO. But instead of loading data one word or one byte at a time, a whole packet of data is loaded at once.
Another point about the endpoint FIFO is speed related. Because data is coming in very fast, double buffering—at the least—is necessary for the packets. Cypress has gone a step further by making this aspect of the device programmable. Endpoints can be double, triple, or quadruple buffered, depending on the amount of data or elasticity that's needed. For example, in a mass storage peripheral, data comes off a read channel at a high rate of speed, and then it's sent onto the USB while the read/write head is moving to the next track. Quadruple buffering is needed in order to make this work.
The designer doesn't really have to become involved in how this works. The part looks like a regular FIFO to the outside world. It has FIFO full flags, FIFO empty flags, and a programmable flag. The fact that it's a "quantum" FIFO (in the company's words) with packets swapped in and out is completely transparent.
The quantum FIFO concept has blocks of 256-by-16 dual-port RAM (Fig. 2). They sit on the USB side while data is loaded or unloaded from the USB. Then the data is swapped across the dotted line (Fig. 2, again) to the I/O system environment when the entire packet is deemed good. The 8051 also has access to this memory, which is used, for instance, for other packet protocols. An example is Ethernet, where a packet might need to be examined before it's shipped out to an application. The 8051 can look at header packets and process them as required.
What may not be obvious here can be studied through a comparison between USB 1.1 and 2.0. When USB 2.0 came along, it required some thought about how to implement the architecture. If Cypress had stayed with the original architecture, it may have included a FIFO on the I/O side and another for the endpoint buffers for USB. But because USB 2.0 is so fast, both of those buffers would have been huge and, thus, increased the cost of the device.
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