[Product Innovation]
Integrated USB 2.0 Chip Extends Its Reach To High-Speed Peripherals
This chip promises designers time-to-market and other advantages when implementing the new 480-Mbit/s standard.
The quantum FIFO idea is an ingenious way to combine those functions so that a FIFO is seen by the outside world and an endpoint buffer is seen by the internal chip. In effect, these are one and the same. In the previous architecture, these were separate memories. As separate FIFOs, it was easy to keep them in different timing domains. Different timing domains are still necessary with this implementation—one for USB and one for the outside world I/O—but that's accomplished in a more intelligent way. In contrast, the designer of a multichip scenario would have to go back to the two-FIFO arrangement, and all of the costs associated with having two large buffers.
The flexibility of the FX2 is enhanced by the general programmable interface (GPIF), which is a programmable state machine. It can generate all the control signals, for example, for an ATAPI hard-disk drive, a Utopia interface for DSL, or an enhanced printer port (EPP) for printers. The key point is that the designer can address all of these different interfaces with the same part, without using any glue logic. This extends to microprocessors too, such as the PowerPC, and digital signal processors (DSPs), as well as PCMCIA devices. Each might have required a different part to be glueless and, thus, cost effective. The GPIF enables the FX2 to adjust for each of these interfaces.
Designers must program the GPIF, but Cypress provides a software tool to generate the appropriate interface. The designer doesn't have to figure out how the interface works. In addition, the company has reference designs to help in this area.
As mentioned earlier, the FX2 comes in three packages. One is the 56-pin SSOP, another is a 100-pin thin quad flat pack (TQFP), and the third is a 128-pin TQFP. The differences in pin count are due to the number of inputs and outputs. The 128-pin package is there just in case the designer has to use external data and address buses and more than 8 kbytes of RAM. This makes the architecture extensible and gives the designer a growth path. The focus for Cypress, though, is on the two smaller packages.
Price & Availability Samples of the FX2 will be available early in the fourth quarter of this year. Pricing varies with package type and program memory size, but all family members will be priced under $10 for low production volumes. Development kits will be available as well in the fourth quarter for $495 each.
Cypress Semiconductor Corp., 3901 North First St., San Jose, CA 95134; phone (408) 943-2600; fax (408) 922-0833; www.cypress.com.
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