Over the last decade, most OEM system designers used FPGAs to implement custom digital logic for system-level prototyping and qualification. Unable to meet production-cost targets with the FPGA, these same OEM designers turned to ASICs for reducing cost during production implementation. Until recently, the ASIC options were limited to cell-based ASIC solutions.
Lately, a new breed of structured ASICs have been introduced as an alternative to cell-based ASICs. The combination of nearly cell-based density, speed, and power consumption, coupled with low NRE costs, short turnaround time, and compatibility, along with existing low-cost design tools, have made structured ASICs the logical choice for applications not demanding bleeding-edge performance. These structured array products are expected to play a major role in the ASIC market in the coming months and years.
The structured ASIC architecture is based on predesigned functional blocks (logic functions, timing generators, memory, and I/O) embedded in a structured manner within the base array. The ASIC’s core area consists primarily of macro blocks for implementing logic functions, and a fixed amount of memory blocks. The memory blocks may be integrated in the functional macro blocks and distributed throughout the array. Or, they may be embedded separately as larger blocks in the array’s core. The core area could also contain specialized embedded blocks, such as timing generators used to optimize the performance and perform frequency-synthesis operations of individual designs implemented with the structured array. Most of today’s structured architectures are flexible enough to further embed additional and more-complex IP blocks, such as a microprocessor core.
Structured Versus Gate Array
Despite its prediffused elements, structured ASICs differ from previous gate-array devices. Gate arrays use prediffused transistors to address manufacturing cycle time. With structured ASICs, the focus is on the design-cycle time and reducing the overall time from design concept to receiving parts. This is why structured ASIC products typically contain built-in test and predesigned power grids. These may not save much in terms of manufacturing cycle time. However, by predesigning them into the silicon fabric, the logic designer doesn’t have to spend the time or buy the tools needed to perform complex test insertion or signal-integrity checks. A structured ASIC presents a "correct-by-construction" approach that directly addresses design-cycle time as well as manufacturing-cycle time—a major enhancement over gate-array products.
Figure 1a depicts one example of a structured ASIC architecture—the AMI Semiconductor XPressArray. In this architecture, the timing generator DLL and PLL functions are predesigned and embedded in the array near the I/O ring. Each of the eight I/O banks in the pad ring is predesigned to accommodate one of several power-supply voltages. The flexible pad architecture also allows each I/O buffer within an I/O bank to be programmed to any one of a spectrum of available I/O standards.
Another important aspect is that the design-for-test (DFT) functions are predesigned and embedded in the device. In addition, the DFT functions in today’s structured arrays are compatible with industry-standard CAD tools. Compared to a cell-based ASIC, this feature reduces development time and NRE cost. In the case of the XPressArray, the DFT functions are predesigned with flexibility by including the DFT scan multiplexer in the macro cell. At the same time, the layout tool can route the connections between the multiplexer and the flip-flop as required for each specific design. This flexibility optimizes the design flow and provides adaptability for designs requiring multiple clock domains—without consuming power for unused flip-flops.
An additional feature is that performance-critical aspects of the physical design, such as clock distribution and power busing, are often predefined. These aspects of a cell-based ASIC design consume much more valuable engineering time, cost, and segments of a development schedule. For example, floorplanning of a structured ASIC is predefined by the fixed placement of the architecture. The floorplanning phase of a cell-based ASIC design can require weeks to months of valuable development schedule, requiring several iterations through the floorplanning process and static-timing analysis.
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