Optimizing between conflicting design goals—such as die size, power, leakage, speed, yield, and cost—is a neverending issue for engineers. Designers need a fast yet accurate means of comparing and visualizing tradeoffs in library characteristics, semiconductor process nodes, memory configurations, and IP. Giga Scale IC's InCyte gives them a specification cockpit, estimation engine, floorplan generator, performance calculator, and comparison display, driven by Giga Scale IC's Technology Macro Modeler. Bundled with a portfolio of libraries (from 90 nm to 0.35 µm) and a broad family of hard and soft IP macros, users can gain insight into available offerings from semiconductor vendors.
InCyte-Specify, designed for estimation and architectural optimization, captures and optimizes the initial chip specification. It's priced at $6000 per year. InCyte-Create, targeted at the chip creation and implementation process, costs from $15,000 per year.
Designers of math-intensive chips for 3D graphics and other applications may want to look at Arithmatica's CellMath line of IP for standard-cell and custom IC design flows. When applied to math-critical blocks in graphics chips, CellMath IP can reduce overall chip area by up to 10% while boosting processing performance.
The CellMath line includes a graphics library, processor library, and configurable instances, all of which form a rich set of application-level functions in billions of permutations. The IP is delivered with gate-level netlists and bit-accurate simulation models. Functions can be tailored for bit widths, speed and area goals, pipelining, and more. Pricing starts at $175,000.
FPGA designers, like their ASIC counterparts, need static timing analysis to find problems before place and route. Hier Design's TimeAhead offers FPGA designers fast feedback on potential timing bottlenecks, enabling them to make early floor-plan adjustments. The timing-analysis environment is tight-ly integrated with Hier's PlanAhead hierarchical floorplanner and its schematic, netlist, and floorplan views. Thus, TimeAhead gives users cross-highlighting from the analysis report to critical paths graphically traced within the floorplan (Fig. 3). PlanAhead and TimeAhead are now sold together as a package, with a time-based license costing $40,000 per year.
Beach Solutions will use DAC to launch Version 3.2 of its EASI-Studio. This tool provides a structured approach to capturing and maintaining design specification data in one place and then validating the data against customizable design and interface rules. Version 3.2 can "watermark" design data as reliable once it's checked and validated.
Aptix and SoftRISC will present the results of a collaborative effort, their voice-over-IP development and prototyping environment based on the ARM PrimeXsys platform. The environment consists of an Aptix System Explorer prototyping environment integrated with SoftRISC VoIP application software. Available in the second quarter, the Aptix environment starts at $80,000, while the SoftRISC software components start at $75,000.
Zenasis Technologies will have two major announcements at DAC. First is version 2.1 of its flagship ZenTime product, a cell-based timing optimization tool that identifies and combines standard cells in critical timing paths and then replaces them with design-specific custom cells. The tool straddles the front and back ends of the design cycle. New features include a three- to four-time increase in runtime speed.
Second, Zenasis' ZenCell Factory 1.1 complements ZenTime. This automated library-cell generation engine can create, layout, characterize, and verify hundreds of combinational logic cells in a matter of days. It can function in standalone fashion or be seamlessly integrated with ZenTime and other tools in an ASIC flow. ZenCell Factory is priced for term-based licensing at $95,000 per year. It runs on Linux and Sun-Solaris platforms.
Another stealth launch in the mold of Forte Design comes via FishTail Design Automation. FishTail's Focus tool takes synthesizable RTL and clock definitions as inputs and automatically generates the design's false and multicycle paths. The resulting "golden" timing constraints, arrived at before the outset of physical implementation, should enable designers to reach timing closure much more quickly. Focus goes for $90,000 per seat per year.
Tool interoperability is a subject of interest to designers in all phases of the design cycle. The Silicon Integration Initiative's OpenAccess Coalition will show a new Verilog reader/writer kit that was jointly developed by Hewlett-Packard and Cadence. The kit is now available for download at www.openeda.si2.org. It lets designers exchange netlist information directly with the OpenAccess design database.
At DAC, the OpenAccess Coalition also expects to deliver the beta release of its OpenAccess 2.2 code. This release of the reference database will offer performance enhancements as well as improved support for a new region-query application programming interface, rules and constraints, data-management changes, and more.
ANALOG DESIGN
The subset of EDA tools for analog designers will see some interesting activity at DAC. More analog tools are appearing, though it remains to be seen whether analog designers will become more accepting of them.
Anasift Technology will exhibit its AMPSO v1.2 analog optimization tool, which is meant for linear amplification circuits such as op amps, analog buffers, comparators, bandgap references, voltage regulators, and others. Inputs to the tool include Spice netlists, model libraries, design requirements, and optimization corners. This tool optimizes and sizes circuits to meet design specifications across all optimization corners. It outputs designs in pure text format and exports the optimized results to users' existing analog design flow.
Designers of high-voltage ICs like LCD and thin-film transistor (TFT) drivers, power-management ICs, motor controllers, and others have specific needs not addressed by many EDA tools. Silvaco's tool suite is intended to fill that gap. At the front end, the Scholar schematic editor drives the SmartSpice circuit simulator, Expert layout editor, and Guardian DRC/LVS/LPE tools. The suite supports legacy models and netlists from other simulators, as well as the Verilog-A language for compact device models and analog behavioral models. A front-end seat of Scholar and SmartSpice starts at $35,000 for a perpetual license.
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