[Design View / Design Solution]
Interfacing FPGAs To High-Speed DRAMs Puts Designers To The Test
High-speed external-memory interfaces need tight timing constraints, DQ-DQS phase management, good signal integrity, and proper board designs.
RESYNCHRONIZATION OF READ DATA TO THE SYSTEM CLOCK Another challenging aspect of DRAM interface design is converting the read data from the DQS clock domain to the system clock domain. Read data from the DRAM is first captured in the DQS clock domain in the memory controller. This data then must be transferred to the system clock domain. To ensure that the DQ signals are captured correctly in the FPGA, designers need to determine the skew between the DQS and system clocks. Minimum and maximum timing analysis must be performed on the following to calculate the skew accurately (Fig. 2):
Delay from PLL clock output to the pin (tPD1)
Clock board trace length (tPD2)
Access window of DQS from clock (tDQSCK from the DDR memory data sheet)
DQS board trace length (tPD3)
Delay from the DQS pin at the FPGA to the I/O element (tPD4)
Micro clock-to-out number for the I/O element register (tCO1)
Delay from the I/O register to the resynchronization register (tPD5).
To find a safe resynchronization window, designers need to calculate the minimum and maximum delay of the system by adding all of the delays (also known as the round-trip delay) listed above (Fig. 3). The resynchronization window can be obtained by using the following equation:
Resynchronization Window = minimum round-trip delay + one clock period − maximum round-trip delay − maximum micro setup and hold time of the resynchronization register
If the resynchronization window falls outside of the system clock edge, the designer needs to use another phase-shifted PLL output clock so that the edge will be within this window. The task of calculating the round-trip delay and estimating the clock phase for the resynchronization clock is error-prone as well as time-consuming.
Many times, designers use trial and error to find out the resynchronization clock phase. Some FPGA vendors provide design aids to reduce or eliminate this trial-and-error process. For example, Altera's memory-controller IP cores come with a round-trip delay calculator that lets designers calculate the resynchronization window for their particular system. Designers can input trace delay and other delay components specific to their system. The round-trip delay calculator will estimate the skew between the system clock and the DQS domain. If a phase-shifted output from the PLL is required, it will also specify the amount of phase shift required to capture data correctly.
Another technique for resynchronization is to use a feedback clock and an additional Read PLL as shown in Figure 4. The board trace for the feedback clock, FB_CLK, from the memory should be the same as the board trace lengths of the DQ and DQS signals. The FB_CLK is connected to the DRAM CLK pin and routed back to the FPGA. The Read PLL phase-shifts the incoming clock FB_CLK so that it correctly captures the read data from the DQS domain to the system clock domain. The phase-shift amount is the sum of the ±tDQSCK value from the DRAM; any board-trace skew between DQS, CLK, and FB_CLK traces; and the delay between the IOE register and Resynchronization register.
SIGNAL-INTEGRITY AND BOARD-DESIGN CHALLENGES Another common challenge associated with memory-interface design is maintaining the signal integrity. The wide bus widths of these interfaces introduce simultaneously switching noise (SSN), which has the potential to cause bit errors. In addition, improper termination or board design can lead to poor signal quality due to crosstalk, signal attenuation, noise, etc. All of these factors adversely affect the system's performance and reliability. So, proper board design is key to building robust memory interfaces. Here are some basic board-layout guidelines for memory interfaces:
Match trace lengths to avoid skew between signals.
Route DQ, DQS, and CLK at least 30 mils away from other signals to avoid crosstalk.
Use one 0.1-µF capacitor per two termination resistors.
Implement precision resistors (within 1% to 2 %).
Use an integrated VTT regulator specially designed for DRAM VTT.
Route VREF at least 20 mm away from other signals.
Shield VREF with VSS on one side, and with VDDQ on the other side.
Furthermore, SSN can be minimized by selecting the right I/O placements, using programmable power and ground pins, slowing the I/O slew rates, and selecting the right decoupling scheme. In a worst-case scenario for a one-DIMM system, as many as 81 drivers (64 data, eight ECC, and nine strobe signals) may be switching states on a memory module. An additional 28 signals may be transitioning on the controller at the same time in a pipelined access.
Traditional methods for providing decoupling involve placing capacitors in convenient locations, based on the routing of the board, and applying some predetermined ratio of capacitors to driver pins. Unfortunately, the higher switching speeds of today's DRAM may render such typical ratios less useful. The critical limiting factor in designing a decoupling system is usually not just the amount of capacitance, but also the amount of inductance in the capacitor leads and the vias attaching the capacitors to the power and ground planes. VTT voltage decoupling should be made very close to the parallel pull-ups on the motherboard. Also, the decoupling capacitors should be connected between VTT and ground.
It's important to strictly follow the board-design guidelines provided by memory and FPGA vendors. To ensure first-time success of the memory-interface design, thorough signal-integrity analysis must be performed on a system level. Tools like HSPICE, SPECCTRAQuest, XTK, and HyperLynx are solid options for signal-integrity analysis. Another recommendation is that designers use demonstration platforms to verify designs before porting them to their systems. This debugging stage is crucial in achieving first-time design success. FPGA vendors provide demonstration platforms and specific design guidelines for interfacing memory with their FPGAs.
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