================================================= EDA Alert e-Newsletter Electronic Design - www.electronicdesign.com February 14, 2006 ================================================= Today's Table of Contents: 1. Viewpoint Exclusive -- Shedding More Light On DFM Signoff 2. DFM Offering Expands To Encompass Lithography-Aware Design 3. Verification Tool Adds SystemC 2.1 Support 4. Spice Simulator Supports Latest Transistor Models 5. Hardware Prototyping System Handles 24 Million ASIC Gates 6. Happenings - DVCon '06 - FPGA '06 - ISQED '06 - DATE '06
******************************************************* TAKE A POLL: In his recent State of the Union Address, President Bush proposed an American Competitiveness Initiative. Which element of that initiative will best prepare the U.S. to compete in the global marketplace?
-- Increased funding for technology research programs -- A permanent R&D tax credit -- More rigorous math/science education programs
******************************************************* Did you miss last week's DesignCon in Santa Clara? Catch up on the EDA side of the event by reading EDA editor David Maliniak's daily show blogs.
******************************************************* ************ 1. Viewpoint -- Exclusive to EDA Alert ************ Shedding More Light On DFM Signoff
By Peter G. Feist, CEO SIGMA-C Software AG, Munich, Germany
As chip costs escalate, the quest for DFM signoff models intensifies. Although everyone is searching for that one sure way to eliminate the respin nemesis, the challenge grows more daunting as process sizes shrink...
******************************************************* Free Webcast: Boost DSP Throughput with Low-Cost FPGAs Wednesday, February 22, 2006 at 2:00 pm ET
Designers are increasingly turning to FPGAs to help accelerate DSP performance and add extra compute power as a coprocessor. Lattice Semiconductor's latest-generation FPGAs have built-in DSP blocks that each contain a pipelined multiplier-accumulator engine. Learn how to implement DSP functions in these latest low-cost, high-performance FPGAs. One lucky participant will receive an ispLEVER Development Tool for FPGA and CPLD design. Register today!
With the Virtuoso Resolution Enhancement Technology (RET) Suite, designers can create IC layouts for sub-90-nm technology that are less sensitive to critical yield-degrading lithography issues. In addition, designs developed with the tools are desensitized to common lithography process variations.
Users can analyze and optimize designs for both performance and yield by examining precisely how target layout structures will appear in silicon. This is achieved through precise modeling of the distortions inherent in sub-wavelength lithography. The suite includes interactive model-based simulation of layout designs, batch and interactive lithography rule checking, lithography yield analysis and optimization, and trial-based optical-proximity-correction capabilities using critical process parameters.
Contact Cadence directly for pricing and delivery information.
******* 3. News ******* Verification Tool Adds SystemC 2.1 Support
Integrated support of SystemC 2.1 is now part of Aldec's latest Riviera simulator. Riviera 2006.02 also offers incremental compilation for VHDL and Verilog design modules, which results in shorter compile run times and improved simulation run times. Thanks to SystemC support, it's now easier for Riviera to interface with third-party tools that already support SystemC. The tool also sports improved handling of SystemVerilog Assertions, better code coverage, and a beefed-up waveform viewer.
Pricing for Riviera 2006.02 starts at $12,450 for floating OS-independent licenses that support Unix, Windows, and Linux.
The latest version of Tanner EDA's T-Spice Pro circuit simulator supports the Penn State Philips (PSP) transistor model. The Compact Model Council recently singled out the model as the next standard for simulating future CMOS transistors manufactured at 65 nm and below. PSP will succeed the BSIM3 and BSIM4 models now in use. It's expected to simplify the exchange of chip-design information. T-Spice Pro, based on an intuitive GUI that runs on Windows-based systems, will continue to support other industry-standard models.
Call Tanner EDA directly for pricing and delivery information.
******* 5. News ******* Hardware Prototyping System Handles 24 Million ASIC Gates
With support for up to 14 LX Family and two FX Family Xilinx Virtex-4 FPGAs, the DN8000K10 ASIC Prototyping Engine comfortably supports emulation of up to 24 million ASIC gates. Source-synchronous low-voltage differential-signaling technology interconnects the system's FPGAs. All chip-to-chip interconnects run at 350 MHz (700 Mbits/s).
When fully configured, the DN8000K10 features 2.6 million flip-flops/lookup-table (LUT) pairs, representing nearly 37 million total available gates (assuming 14 gates for a flip-flop/LUT pair). The system includes a full complement of I/O facilities, as well as space for up to 8 Gbytes of external memory. It comes standard with a metal carrier and power supply.
Prices start at $22,000, with delivery in less than three weeks.
The DINI Group ==> http://news.electronicdesign.com/t?ctl=20C8D:484C79
************** 6. Happenings ************** Design And Verification Conference and Exhibition (DVCon '06) Doubletree Hotel, San Jose, Calif. February 22-24, 2006 http://news.electronicdesign.com/t?ctl=1C43B:484C79
International Symposium on Field-Programmable Gate Arrays (FPGA '06) Hyatt Regency Monterey, Monterey, Calif. February 22-24, 2006 http://news.electronicdesign.com/t?ctl=1C43C:484C79
Design Automation and Test in Europe (DATE '06) ICM Messe, Munich, Germany March 6-10, 2006 http://news.electronicdesign.com/t?ctl=1C43D:484C79
International Symposium on Quality Electronic Design (ISQED '06) Doubletree Hotel, San Jose, Calif. March 27-29, 2006 http://news.electronicdesign.com/t?ctl=1C43E:484C79
Advertising/Sponsorship Opportunities: Bill Baumann mailto:bbaumann@penton.com
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