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With 65-nm processes going mainstream, designers will soon turn their attention to the 45-nm process node. And if you think 65 nm was tough to contend with in the fab, the 45-nm plateau opens the door to even uglier possibilities—trashing yields and turning ever-so-painstakingly crafted layouts into something resembling oatmeal running down a wall.

In 2007, it'll be imperative for designers to embrace technology to address parametric yield. Statistical static timing analysis, statistical leakage analysis, design optimizations based on lithography, and simulation of chemical-mechanical-polishing (CMP) process steps are all elements of what make up design-formanufacturing (DFM) techniques.

Unprecedented complexity in today's system-on-a-chip (SoC) designs is driving foundries to the limits of classical CMOS scaling. In addition, the debut of immersion lithographic processes means that designers face new challenges in terms of high numerical-aperture and polarization effects. Systematic and parametric defects now outrank random defects as the primary causes of yield loss.

Designers must look for predictability in silicon processes and real connections between design and manufacturing. Tool flows that make it possible to perform yield analysis before fabrication, or even yield grading based on a given set of process conditions, will prove critical. That's because design teams and foundries will be able to share the necessary data for the sake of yield (see "Dealing With Shades of Gray," p. 64).

Physical implementation flows will become more "process-aware." They're already beginning to incorporate fab-specific parametric data. But truly effective DFM will require an approach spanning the entire design and implementation flow.

It'll be very difficult, however, for the DFM puzzle to be solved in the implementation process. Assessment of a number of process variabilities can't be accounted for during the layout generation. Thus, look for two new breeds of EDA tools to emerge.

One breed will be a comprehensive platform that analyzes the impact of process variability. Such a platform will combine all manufacturability- and yieldrelated analyses and become the tool for implementing the "DFM sign-off" (or socalled "yield sign-off") step in the design flow (see the figure). The second new breed will involve post-place-and-route multipurpose layout "polishing." These tools will repair or optimize design layout to make it more robust and less sensitive to process variations.

Also, look for a move to in-context, model-based electrical DFM analysis tools that incorporate fab data on lithography, reticle-enhancement technology, optical-proximity correction, CMP, masks, and etching.

Layout Automation
Layout needs further automation. Look for new technology that automates the layout of specialized designs, such as memories, datapath processors, and imaging and display ICs. All of these exhibit layout characteristics that fall outside of traditional ASIC design styles. At present, layout of such devices is typically performed manually.

Such technologies will drive manual "polygon pushing" techniques toward obsolescence. Further, yield issues will accelerate the adoption of automated layout techniques. These methodologies will integrate design and analysis, using layout automation to manage the yield information from local layout analysis.

Sharing The Load
Thanks to rising mask and wafer costs, some systems houses have held off on using state-of-theart process technologies. This year, more integrated device manufacturers (IDMs) and fabless semiconductor firms will share the upfront costs of a mask set and wafer run across multiple designs, including those from other companies.

Multiproject wafer (MPW) services are available from major fabs and specialists in such services, usually working with fabs like IBM, AMIS, and TSMC. For each mask set and wafer run, users only pay for the physical area of the masks and wafers they use, so costs can be dramatically lower than they would be with a dedicated mask set and wafer run.