The industry is moving to the 45-nm process technology node. As with the 65-nm node, this migration will be pioneered by foundries
partnering with first-tier movers such as large fabless companies
and integrated device manufacturers (IDMs). The move to 45 nm,
regardless of the application (e.g., FPGA or RF), poses a number of
challenges.
Increased process complexity to boost device performance: Since
traditional device scaling methods can no longer be applied due to the
physical limitation of gate dielectrics material, many mobility enhancement techniques have to be introduced in this node, such as silicon
germanium (SiGe), compressive and tensile nitride films, and stress
memory effect for poly gates. To introduce these new techniques to
boost device performance, new integration schemes, new materials,
and new tools have dramatically increased the complexity of the
45-nm process.
Defect issues: New fabrication techniques often result in defect
issues. As an example, consider how UMC's fabrication of working
45-nm SRAM identified potential defect issues associated with
immersion lithography. Such issues include resist/topcoat selection
and recipe optimization for each layer, compatible etch recipes to achieve the final resolution, and alignment limitations imposed by
current scanners before immersion lithography's full maturity. Achieving a workable 45-nm yield requires ongoing identification of device
optimization through various ultra-shallow junction techniques as well
as back-end cleaning techniques to maintain the dielectric k integrity
while also maintaining good defect control. Device adjustment,
induced by the introduction of new materials such as SiGe into the
PMOS source/drain area, may also be necessary.
Partnerships: Close collaboration between the manufacturer and
tool/equipment partners is necessary to address the hardware limitations and issues that may arise during high-volume manufacturing. A
close partnership with customers also is necessary to maximize
process compatibility with their product needs.
As the chip world steps up its pace toward 45-nm adoption, overcoming these challenges while enhancing process margin and manufacturability will be critical to ensuring its success.
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