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Due to the growth in the consumer and wireless markets, low-power design is becoming a pervasive driver in IC design, verification, and implementation. The challenge lies in achieving timing closure while adopting advanced low-power and mixed-signal techniques—while improving time-to-volume and yield.

Design for manufacturing and/or yield (DFM/DFY) remains the biggest challenge because of the increasing need to improve parametric and manufacturing yields. In 2008, designers will incorporate variation-aware models of lithography, chemical-mechanical polishing (CMP), etch, and stress effects during the implementation phase.

Meanwhile, the cost associated with excessive margins in multimode, multicorner designs will drive adoption of statistical optimization and analysis techniques. Mainstream DFM adoption will begin, but it largely depends on foundries and EDA companies making real investments in foundry-validated models and DFM-aware design tools.

Life at 45 NM
In 2007, the industry began including statistics in process characterization, modeling, and design analysis. Manufacturers have started including limited statistics in Spice models and providing statistical cell models to enable a statistical timing-analysis (STA) flow.

Designers have started adopting statistical analysis, the most common motivation being to reduce pessimism or overguardbanding. The process of STA adoption will accelerate in 2008, especially as 45-nm flows begin to come online.

The 45-nm node carries heavy implications for EDA, because it’s a point where the traditional tool flow for physical design and verification hits its limits. This is a result of greater sensitivity to manufacturing process variability, an explosion in the number of corners that must be analyzed to optimize a physical design, and the sheer size and complexity of designs at the 45-nm node.

To meet the new challenges, EDA vendors will invest in new architectures and technologies that address the demands of 45 nm and beyond. For example, traditional place-and-route tools are running out of steam at 45 nm. Process variability must be considered explicitly during implementation in the form of DFM models so layouts can be optimized for manufacturability.

New core compact data models are needed to enable efficient processing of designs with 150 million or more gates. Also, new timing representations and engines are needed to enable simultaneous analysis and optimization for all modes, corners, and DFM constraints to boost performance and minimize area.

In fact, the physical verification process has evolved to include a greatly expanded set of design rules and a host of DFM checks (see the figure). Typical DFM analyses include critical area analysis (CAA), critical feature analysis (CFA), CMP analysis, and lithography simulation and process checking.

For real effectiveness, recommended design rules and DFM results must be ranked and presented as intuitive visualizations that enable designers to make rapid tradeoff decisions in a manner similar to traditional Pareto analysis. Results should be fed back to the P&R engine so that once the designer sets the goals, enhancements can be made automatically.

As in other areas of EDA, expect tighter relationships between foundries and their DFM partners, leading to better products and better yields. We will also see a continuation of the welcome trend of DFM companies working together to integrate products and promote industry standards such as the Si2 Design For Manufacturability Coalition.

PDKs Hit the Street
The silicon foundries will begin providing the first interoperable process design kits (PDKs) for analog and custom design in 2008. Until now, PDKs have tended to include PCells that worked with only one vendor’s tools. While this was convenient for the foundry, it made life difficult for designers as well as for EDA vendors whose tools were not supported. These excluded vendors had to recreate each foundry PDK for use with their tools.

The emerging OpenAccess database makes possible interoperable PDKs, which do not exclude any vendor or user. Interoperable PCells work with any OpenAccess tool from any vendor. This is a major advance for users, who will be able to choose the best tools for their IC project.