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Tighter power regulations and safety issues are demanding efficient and intelligent power supplies that can be monitored externally and manufactured cost-effectively, with minimal hardware changes.

Power-supply engineering advances have shown that digital control of the power-conversion feedback loop enables designers to create more accurate and reliable power supplies with increased power density, at lower costs and with faster time-to-market. These digital power supplies are easily customizable at any time during production because changes can be made in software, rather than hardware.

Using analog feedback circuitry still makes sense in power supplies with less than 100 W in dc-dc and less than 250 W in ac-dc ratings. However, in high-featured, elevated-rating power supplies, digital control of the power- conversion feedback loop becomes critical, since it overcomes most of the limitations sometimes imposed by a fixed analog approach.

For example, a capacitive load may significantly affect a power supply’s stability. Analog feedback systems can be designed to handle a capacitive load, but major changes in the capacitance of the load could exceed the phase and gain margin of the design. The advantage of a digital feedback system is the ability to change compensation on the fly, which allows the feedback to compensate for a wider variation in load characteristics in real time.

THE SHIFT TO DIGITAL
Until recently, digital feedback systems only saw limited use, due to their perceived complexity, the cost of the DSP required, and the limited capabilities of the DSP peripherals. However, through education, the perceived complexity is slowly fading, and the digital signal controller’s (DSC) arrival has helped to alleviate the problems associated with cost and peripheral capability.

DSCs combine the look and feel of an MCU with a DSP’s calculation and processing capabilities. CPU design incorporates the math functions typically found in DSPs, while the functionality and flexibility of the peripherals trace their lineage to embedded controllers. The resulting DSC exhibits the math performance of a DSP, while retaining the flexibility and complex, coordinated features of the peripherals. DSCs significantly ease design complexity, without burning CPU performance to achieve it.

In fact, with these features, designs using DSCs are actually much simpler than DSP design because many DSCs come with power-supply-friendly peripherals onboard. Such peripherals include counter-based pulse-width-modulation (PWM) modules, analog comparators, and analogto- digital converter (ADCs). Hence, analog comparatorbased feedback and ADC sampling are enabled. These capabilities, coupled with fast multiplication in a singleclock cycle, allow DSCs to easily handle the high execution rates needed for power-supply control-loop software.

The DSC’s performance capabilities, coupled with the lower switching frequencies of high-power designs, enable even a moderately performing DSC with the appropriate peripherals to easily handle multiple control loops. This means that a single chip not only improves the response characteristics of the supply, but does so for multiple independent outputs simultaneously.

Before starting a power-supply design, designers must make three basic choices:

1. What will be the design’s topology?
2. What will be the operating mode?
3. What will be the control methodology?

The topology is driven primarily by the design’s input-to-output voltage ratio. The operating mode is driven by the topology and the required output current, as well as by the costs associated with the components. Finally, the control methodology is typically driven by the available technology and, to a lesser extent, component cost. Let’s examine each of these choices, with an eye toward how the use of a DSC will affect the decision.

TOPOLOGY
As mentioned above, topology is driven primarily by the input-to-output voltage ratio of the design. Designs with a higher input voltage typically use a buck topology, while lower-input-voltage designs usually go with a boost topology. However, another factor that often drives the choice of topology is the availability of a PWM controller with the requisite features, which is compatible with the chosen topology. After all, if a designer can’t generate the appropriate switching signals, a switch-mode power supply (SMPS) isn’t possible.

This is where the DSC steps in. Because a DSC’s peripherals are programmable, it’s possible to generate a single PWM output, two or more phases of PWM output, half-bridge drive outputs, or even a full H-bridge drive output. In fact, due to the programmability of the DSC’s peripherals, a given topology needn’t remain static.

It’s well within the capabilities of a DSC to switch from a single phase, to two phases, and then to three phases, all while maintaining the appropriate phase shifts between phases. Some DSCs even go so far as to include deadtime control between bridge outputs for the purpose of preventing shootthrough currents in synchronously switched designs (Fig. 1).

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OPERATING MODE
The next area to consider is the operating mode. Typically, analog designs operate with either a continuous inductor current or a discontinuous inductor current. Both options offer distinct advantages. A discontinuous current-mode design can maintain voltage regulation, even if the output current drops to zero. A continuous design utilizes smaller magnetics and maintains tighter control on the output-voltage ripple. Until recently, it hasn’t been possible to effectively combine these modes, due to their different feedback requirements.

However, a DSC’s programmable peripherals can be reconfigured on the fly while the design is operating. This means that a DSC-based design can switch between operating modes, switching to continuous mode when the output current is sufficient for stable operation and then switching to discontinuous mode when the output current drops too low.

While an analog design would certainly be able to perform a similar transition, it would require two feedback paths (one for each mode), and thus, there would be a momentary glitch at the transition. So, the DSC has the added advantage of requiring just a single feedback path. Due to the software basis of the feedback, it’s even possible to preload the storage elements of the feedback filter, avoiding the transition glitch (Fig. 2).

CONTROL METHODOLOGY
The final design choice is the control methodology of the design—whether to use voltage- or current-mode control. Traditional analog SMPS designs use either of the two control techniques, with the final choice typically being driven by cost and available technology.

Voltage-mode control, which is the older method, was found in most early SMPS designs. It uses a ramp generator and a voltage comparator to translate the error signal from the error amplifier/ loop filter into a PWM pulse width. Simple voltage-mode control suffers from three basic limitations. First, there’s no current limiting to protect the circuit components. Second, it responds slowly to input or output transients. And third, it produces a feedback loop that’s inherently unstable.

Current-mode control is a better and safer control method, consisting of a dual-loop format. The inner current loop is designed to charge the inductor to a peak current specified by the outputvoltage loop. The outer loop is similar to the feedback loop of voltage-mode control in that it monitors the output, phase/ frequency-compensates the feedback, and regulates the energy transferred by the current loop.

Because the inner loop regulates the inductor current on a cycle-by-cycle basis, the inductor essentially has no memory of the previous pulse and doesn’t carry energy over from the previous cycle. It additionally offers peakcurrent protection for the transistors, eliminates “ratcheting” in the magnetic components, rejects input-voltage variation, and affords easy control-loop compensation.

An efficient implementation of currentmode control in digital SMPS designs lies in using a DSC that features an onboard PWM peripheral, which works in the same way as a current-mode PWM generator (Fig. 3). The difference lies in the output of the digital feedback. A voltage-mode design uses the feedback to directly control the PWM’s duty cycle. In a current-mode design, the comparator-based pulse-termination capability of the DSC’s PWM regulates the pulse width, based upon current feedback, and the output of a digital-toanalog converter (DAC) that’s driven by the digital feedback.

Current-mode control is implemented by calculating the SMPS design’s required PWM frequency and maximum duty cycle, and then configuring the PWM counter with these parameters. This sets the maximum duty cycle and pulse frequency of the system. Next, the design must adjust the reference DAC output to handle the expected maximum range of the current-feedback signal. In doing so, you will be able to provide the highest resolution in controlling the PWM duty cycle.

Finally, the specific proportional- integral-derivative (PID) software routine, required to control and stabilize the system, must be developed. This routine must provide the appropriate feedback for stability, based upon the voltage feedback from the ADC. Moreover, it must compare the feedback against its own internal digital reference and output the desired current setting to the DAC that’s generating the comparator reference (Fig. 3, again).

DIGITAL LOOP CONTROL
A key factor to consider when using a DSC for an SMPS application is to ensure that the onboard PWM module provides adequate resolution for the power-supply design. The resolution and speed of the ADC onboard a DSC, which provides the system with status (feedback) to the control loop, should also have adequate resolution.

Next, it’s important to choose a DSC that has onboard analog comparators of sufficient speed for the pulse widths to be generated. ADCs could be used in place of the comparators for terminating the PWM pulse, but they would have to continuously monitor and process signals. This is a waste of processing power, since the monitored signal is merely being compared to a fixed limit. High-speed analog comparators free the processor and ADC to perform other, more valuable tasks, while enabling the DSC to perform powersupply fault and currentlimiting functions.

Furthermore, it’s useful to have a DSC with an ADC module that provides independent sample-and-hold circuits. This allows the DSC to sample multiple voltages or currents simultaneously and at precise times. As a result, even transitory signals can be sampled, and it helps reduce system costs. It’s even better if the ADC can sample asynchronously, because it can then support multiple control loops operating at different frequencies, such as a powerfactor- correction (PFC) circuit running at 70 kHz and a dc-dc conversion block running at 250 kHz.

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PID ALGORITHM IN SMPS DESIGNS
Using the PID algorithm, the proportional, integral, and derivative errors of the actual versus the desired output voltage are combined to control the PWM duty cycle. There are three basic forms of the algorithm:

• Series, or interacting
• Parallel, or non-interacting
• Ideal parallel

The PID algorithm can be deployed in both voltage- and current-mode control loops. Also, complex DSP programming skills aren’t required with DSCs, because they offer DSP functions as peripherals within the familiar MCU environment.

Duty cycles greater than 50% may present current-mode stability problems. However, you can easily handle this through the PID software, which sets the required current level. As a result, it’s trivial to scale the DAC value. This makes implementing slope compensation digitally easier than using the analog technique, which requires a ramp generator synchronized to the PWM pulse and a summing junction in which the ramp adds to the current feedback.

The result of this technique is a current-mode SMPS design that’s based on economical, lower-MIPS DSCs, as opposed to a fast controller running at 1 to 2 BIPS. For example, the dsPIC30F202X DSC from Microchip features high-resolution digital PWM generators, an ADC rated at 2 million samples per second, high-speed analog comparators with associated 10-bit reference DACs, and a 30-MIPS, DSP-capable controller (Fig. 4).

The PID control loop is the core of the control software (Fig. 5), which runs under an ADC interrupt on a fixedtime basis. System functions such as voltage ramp-up/ down, error detection, feed-forward calculations, and communication support routines should be executed in the “Idle Loop,” in order to reduce unnecessary work within the PID control software.

The PID loop is the most timecritical portion of the software. So, to make sure the DSC’s resources are used efficiently, the loop should use no more than approximately 66% of the available processor bandwidth. This should leave the design with sufficient horsepower to handle idle-loop functions like communications, or support functions like softstart and sequencing.

In a 30-MIPS, DSC-based SMPS application, this translates to a PID loop comprising 30 instructions, with an execution time of approximately 1 µs. Keeping to an iteration rate of 500 kHz (or 2 µs), the PID-control loop uses one-half of the available processor bandwidth, or 15 MIPS.

FREE TO INNOVATE
There are several advantages to power supplies that utilize digital feedback control. Mostly, they involve flexibility and giving a designer the freedom to innovate. As noted above, a frequent concern in a design is the availability of the appropriate technology to implement the design. The advantage of the DSC is its configurability, which lets the designer create the appropriate technology that’s specific to the required design.

For example, a power supply may need to coordinate multiple output voltages during startup and shutdown, or perform load or current sharing among a group of independent powerconversion modules. In these cases, digital feedback control can provide such functionality at no additional cost. Customizing power supplies in these ways using analog components can only be very expensive.

Another advantage is the ability to change a system on the fly, or “hot-swap” capability. For example, if a power module in a telecom or other mission-critical application fails, a service technician can replace the defective power module with a new one while the system continues to operate. This “hot-swap” capability can be very expensive using analog parts, but quite cost-effective if the power supply is digitally controlled by a DSC.

Moreover, if a power supply must be able to adapt to changing requirements, a DSC can be easily reprogrammed. If it’s an analog-based power-supply design, you must start over with a new module. In addition, because of on-chip flash memory, DSCs can enable a simplified power-supply production assembly line. That means a single hardware design can be configured for multiple customer voltage and/or current requirements.

Further, power-supply trimming and calibration can be performed by programming the DSC’s flash memory. This eliminates trim pots or laser trimming of resistors. Digital power supplies can also load test-friendly software for board test, or make multiple custom products based on the same DSC hardware platform.

CONCLUSION
The bottom line is that the benefits of digital power conversion are numerous, and designers can now enjoy them in an easy and cost-effective way by using DSCs with power-supplyfriendly on-chip peripherals. Digital power frees designers to innovate and design power supplies with increased reliability, flexibility, and transient response that can also be easily customized at the end of production through firmware, rather than hardware.