Improvements to the core engine technology behind Synopsys’s HSpice simulator, combined with multi-threading capabilities, gives the tool new life in terms of performance for complex analog and mixed-signal designs. As a result, circuit designers can now run HSpice post-layout simulations up to three-times faster on single-core processors and up to six-times faster on four-core processors than previous versions. The changes take effect with the March 2008 release of the tool.
The latest version of HSpice delivers improvements in the symbolic dc operating-point convergence algorithm, transient time-step control, netlist parsing and model performance. These enhancements accelerate overall simulation throughput on single-core computers.
Previously, HSpice’s multi-threading capabilities allowed circuit designers to quickly simulate large pre-layout designs. With the March 2008 release, Synopsys has extended HSpice multi-threading capabilities to enable simulation of large post-layout designs containing in excess of one million resistive and capacitive parasitic effects. As a result of these enhanced multi-threading simulation capabilities, fully extracted post-layout designs can now be simulated in just hours instead of days.
Contact Synopsys directly for pricing and delivery information.
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