Earlier this spring, Taiwan Semiconductor Manufacturing
Company (TSMC) revealed its 40-nm semiconductor process
technology. Its portfolio includes embedded DRAM, mixed-signal,
RF, and multi-project wafer (MPW) prototyping. The process improves
gate density by a factor of 2.35 over 65 nm. It also reduces active power
usage up to 15% over 45 nm and provides the smallest SRAM cell
size and macro size in the industry, according to the company. The
process is available in both general-purpose and low-power versions.
Companies that choose TSMC as a manufacturing partner receive full
design services plus a design ecosystem that provides verified thirdparty
IP, third-party EDA tools, and TSMC-generated Spice models and
IP. TSMC expects the first wafers to show up in the second quarter.
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