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Falling FPGA prices and ever-improving tools make FPGA development more palatable to designers who aren’t well versed in this arena. Likewise, the increased number of choices and improved sophistication of soft processor cores for FPGAs create new options for developers who would otherwise look only at stock, offthe- shelf microcontrollers.

There are many reasons why designers should consider FPGAs as a development and deployment platform. Processors come and go, but more intellectual property (IP) developed for FPGAs can be migrated to newer chips. It’s even possible to move between vendors, though developers often take advantage of features that may be unique to a particular chip. Many companies use FPGAs to deliver pin-compatible FPGAs for legacy microcontrollers.

That’s why FPGAs are often the ideal path to take when developing new systems. They can employ a collection of standard peripherals around a standard processor core, such as the venerable 8051 in addition to custom IP. Even multicore solutions are easy to build, though they tend to be cooperative cores rather than symmetrical-multiprocessing (SMP) systems. Applications that require SMP are better addressed by standard multicore processor chips such as those from AMD and Intel.

Software developers favor standard cores, especially those that match existing microcontrollers. Such matches allow common development tools to be used, which can be more critical to success than the optimum performance provided by a custom processor architecture.

Still, enhancing a standard core by adding a few registers or instructions often delivers an interface to custom IP that significantly improves performance, reduces power consumption, and makes many applications practical.

Designing an FPGA system-on-a-chip (SoC) with standard component peripherals is relatively simple. For example, the ARM Cortex-M1 core is easy to incorporate in Actel’s Libero integrated development environment (IDE) schematic layout (Fig. 1). The ARM Cortex-M1 is specifically designed for FPGAs. It supports the full ARM Cortex instruction set.

FPGA vendors have their own schematic design tools. Lattice Semiconductor’s ipsLever handles the company’s FPGAs and complex programmable logic devices (CPLDs). The first step of the development process is complete upon creation of the initial system design. The next step is to move the design onto the FPGA and then write software. Given the flexibility and range of chip options, this can be a significant task. However, it may be easier than you think.

KITS KEEP CODERS CODING
FPGA development kits that target developers who prefer hard or soft processor cores are very common. While most FPGA kits can handle one or more cores, they’re specifically designed to get programmers up and running with a minimum of fuss.

Most FPGA development tools will generate the corresponding header and source code files needed for software development based on the system design. Some extend the task further so that downloading applications to the FPGA’s memory is part of the development process.

Many FPGA development environments use their own IDE with a separate IDE for software development. The separate IDE often is based on the open-source Eclipse IDE with C/C++ development tools (CDTs). There’s some movement toward using Eclipse as the platform for other FPGA development tools.

Altera’s Nios II Embedded Evaluation Kit, Cyclone III Edition, illustrates the trend of providing kits that resemble kits designed for conventional microprocessors (Fig. 2). The LCD screen and removable flash memory are combined with the Cyclone III FPGA to deliver a software platform that can be easily customized using Altera’s Quartus II and SOPC Builder.

The Nios II IDE provides software development support for the 32-bit Nios II soft core. For demo purposes, developers can simply write applications for the Nios II and then run them from the flash memory in an afternoon. Of course, developers can opt to completely redesign the FPGA’s contents.

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A more conventional board approach is found in Avnet’s $495 Xilinx MicroBlaze Starter Kit, which includes the Linux for MicroBlaze DVD plus a Spartan-3A DSP XC3SD1800A edition board (Fig. 3). The DVD features PetaLogix Petalinux and Lynux- Work’s BlueCAT Linux distribution and tool chains, including support for the MicroBlaze memory management unit (MMU). There’s plenty of room on the DVD for video and instructional material in addition to the operating system and tools.

The board has Gigabit Ethernet support, a serial port plus 128 Mbytes of DDR2 SDRAM, 16 Mbytes of configuration flash, and 64 Mbits of serial peripheral interface (SPI) configuration flash. It also has JTAG, a System ACE module, and Eridon debug connectors. Similar to Altera, Xilinx provides its Integrated Synthesis Environment (ISE) for hardware development and an Eclipse-based Embedded Development Kit (EDK) for software development.

Altium’s Altium Designer takes an integrated approach to tools. It can handle a wider range of design chores, including printed-circuitboard (PCB) layout. Altium Designer also can be used with the company’s NanoBoard platform (see “System Design Environment Goes ‘Soft’” at www.electronicdesign.com, ED Online 18334).

This platform differs from most in that it supports all major FPGA vendors’ product lines. Even more impressive is its ability to swap chips and use the same FPGA IP, assuming it doesn’t take advantage of vendor/chip-specific features.

Sometimes, developers will exploit the features of FPGAs. For example, they’ll use one for development that programs faster, while deploying another with better power or performance features. Altium also takes the development platform to deployment. The Industrial Handheld Unit can use the same plug-in modules as the NanoBoard platform (Fig. 4).

Most kits come preconfigured with a soft or hard core plus a complement of standard peripherals. Software developers can program the system strictly using the software-development tools without having to contend with FPGA tools, but this often defeats the purpose of an FPGA platform. Still, it highlights how a software developer’s exposure to hardware configuration can be minimized.

An interesting alternative to configuring the FPGA and then matching it to the hardware interfaces and connectors comes by way of Eridon’s UnifiedLogic Development Platform (see “Use New Hardware To Get Your Job Done Faster,” ED Online 17905). It has a Xilinx Spartan-3A or Virtex-II FPGA-based board at its center, along with multiple connectors that can be used with an array of standard interface uCard modules for connections to Ethernet and RS-232 serial ports (Fig. 5).

The interface modules include a flash-memory device that can be read by the system at configuration time. The Eridon IDE takes this into account and then provides interfaces to be incorporated into a design or to verify that a design’s requirements are met. Modules may be daisy-chained with each module utilizing an arbitrary number of signals. The configuration information notes the functionality of the modules and the number of signals so the system knows what device is attached to a particular FPGA pin.

UnifiedLogic also addresses real-time operating systems (RTOSs) and device synthesis, providing a more robust environment for development and debugging than most alternatives. Altium Designer has a similar approach with more support on the PCB and FPGA design side. However, it lacks the explicit operating-system support found in Eridon’s solution.

Eridon’s approach even includes an online cost-estimate calculator. It matches the menu-style selection of peripherals versus the drag-and-drop schematic capture or the more exacting RTL/ HDL design used with most FPGA design tools.

HARD AND SOFT
FPGA vendors can deliver a host of standard soft cores (see the table). Xilinx also offers PowerPC hard cores with better performance. It’s possible to mix and match cores, which often garners better results than using a large or more sophisticated alternative.

One good example is Actel’s CoreABC (Amba bus controller). This tiny 159-tile core is just 1/20th the size of a 32-bit Cortex- M1. Also, this free controller is ideal for handling interfaces or for supporting FPGA IP. The CoreABC can operate alone, but a more typical scenario has one or more working in conjunction with a power core.

FPGAs enable designers to choose a core that’s relatively independent of peripherals. This means a designer could choose, say, the fault-tolerant version of the LEON3 processor for systemcritical applications.

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When choosing a core, devlopers must consider whether a legacy architecture is a requirement. One reason for the vendor-specific cores such as Altera’s Nios II and Xilinx’s MicroBlaze is that the vendors designed the architectures to take advantage of their FPGA’s characteristics.

In the past, choosing a legacy architecture often meant that tools, operating systems, and experienced developers would be more readily available. These days, vendor cores have been around long enough to have all of these. In addition, standard development platforms like Eclipse means software developers will already be familiar with the tools.

Another tradeoff to consider is on-chip and off-chip memory. In many instances, memory will be dictated by the application, such as when there’s a need for large amounts of off-chip memory. Often enough, though, a single-chip FPGA solution is viable and comparable to a single-chip microcontroller solution. In fact, given the FPGA’s flexibility, a single-chip FPGA solution is typically better than using a microcontroller that will require additional support chips.

No MMU is required for uCLinux. In fact, it’s often used with FPGA soft cores that lack MMU support. The more general availability of MMU support with cores such as Xilinx’s MicroBlaze, ARM’s Cortex-M1, and LEON3 allow full-blown Linux to be supported, as well as a range of other higher-end operating systems.

BETTER DEBUGGING
Going with one or more FPGA soft cores can have other development advantages over a standard microcontroller-based solution. This is true in debugging because FPGAs can be programmed with additional debugging hooks that are able to be removed for production units. Therefore, use of a smaller, less costly FPGA is possible, too.

Most soft cores can be equipped with the standard breakpoint hooks and even instruction trace facilities. Other features include logic analyzer-style trace support for other soft components within the FPGA, which can often be synchronized with instruction trace. Computex provides trace probes for Xilinx’s MicroBlaze, as well as logic-analyzer-style support.

Another neat trick offered by some FPGAs is the ability to read the status of almost any register in the system without the need for additional trace support within the FPGA fabric. Xilinx FPGAs allow the JTAG port to read while the device is running.

Almost a third of all hard-core and soft-core FPGA designs incorporate multiple cores. Standard interprocessor communication IP is often available from the vendors, and it’s usable in operating systems and applications. For example, Xilinx features shared or dual-ported memory and hardware semaphores.

Shared memory is more common than SMP configurations due to its simplicity. Most tools automatically generate the source files to support the interfaces, such as hardware semaphores, but not any higher-level communication facilities.

If your custom IP isn’t too complex and you’re looking for an 8-bit core, consider Cypress Semiconductor’s PSoC. It can handle a wide range of chores and includes mixed-signal support (see “Mixed-Signal Processors Can Aid Visual Robotic Development,” ED Online 18513). The PSoC isn’t as flexible as an FPGA, but its customization greatly exceeds that of a standard microcontroller.

Developers use PSoC Designer to configure the digital and analog interfaces. It’s similar in functionality to most FPGA tools like Xilinx’s ISE, but much simpler and easier to use. The PSoC Express development tool, which employs a graphical programming language, is even easier to use.

An FPGA may not fit all design requirements. Still, developers may discover that it can be a desirable alternative to standard microcontrollers.