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High-brightness LEDs (HBLEDs) are making inroads into more traditional lighting applications that include a dc distribution system (for example, 24-V MR-16 track lights). HBLEDs are more efficient, and they have a potentially longer lifespan than do halogen or xenon lamps.

Because hysteretic controllers are inexpensive, simplify lighting designs, and require no compensation networks, they’re well-suited for driving HBLEDs. Hysteretic controllers usually have a pulsewidth- modulator (PWM) input that enables a pulse train of varying duty cycle to provide the dimming function. One problem, however, in converting a traditional lighting system is that many dimmers provide a 1- to 10-V dc signal rather than a PWM signal. Also, to increase the HBLEDs’ operating lifetimes, a controller should provide temperaturebased current foldback.

Converting a dc voltage to a PWM signal is easy. The PWM signal appears at the output of a comparator when you apply the dc voltage at one input and a triangle wave at the other. Headaches can arise, however, when trying to align the triangle wave with the control voltage. You need a linear relationship between duty cycle and control voltage, with a 0% duty cycle at the minimum control voltage and a 100% duty cycle at the maximum.

The circuit in Figure 1 includes the hysteretic controller, U1 (MAX16820); related power components; and a control circuit based on a quad op amp, U2 (LMX324). U1 drives five HBLEDs from a 24-V source, using only inductor L1, MOSFET Q1, and catch diode D1. A sense resistor (R1) sets the current to 0.5 A. U1 turns Q1 on whenever the current-sense voltage drops below 190 mV and turns Q1 off when that voltage exceeds 210 mV.

Hysteretic controllers have no clock and require no external compensation. U1 also provides a regulated 5 V to power the PWM conversion circuitry. Figure 2 illustrates the currentsense waveform corresponding to a small “ON” time in the PWM signal.

The difficulty in converting a control voltage to a PWM signal involves setting the triangle wave’s peak and valley voltages to closely match the corresponding maximum and minimum values of the control voltage (V_CNTL). Two of U2’s op amps generate the triangle wave, which oscillates between an upper voltage level set by the R7-R8 divider and a lower voltage level set by the divider formed by R7 and R8 in parallel with R9. U2’s output is a 50% duty cycle, rail-to-rail square wave. Setting U2b+ equal to VCC/2 causes U2b’s output to integrate the square wave, producing a symmetrical and linear triangle wave. R10 and C4 set the operating frequency.

Achieving 0 V at the valley of the triangle wave is difficult, because U2b’s output has a worst-case minimum of 60 mV. We therefore chose a valley of 250 mV and a peak of 2 V. Because V_CNTL ranges from 0 to 10 V, R12-R13 divides V_CNTL by 5. This limits the reduced control voltage, V_RED, to 2.0 V and thereby matches the triangle wave’s peak voltage.

U2d creates the PWM pulse train by comparing the triangle wave to V_RED. The triangle-wave valley is 250 mV, so the PWM signal remains at 0% until V_CNTL reaches 1.25 V. This action causes a small offset error that’s most pronounced at low values of V_CNTL, but it also confers an advantage by guaranteeing an OFF position. Figure 3 shows how the triangle wave converts the divided control voltage into a pulse-width-modulated waveform.

Op-amp U2c provides the temperature-based current foldback. The R4-R5-R6 divider delivers 1.5 V to U2c’s noninverting input, which is almost a diode drop below the triangle wave’s peak (2 V). Thermistor R2 (a resistor with negative temperature coefficient) is nominally 100 k? at 25°C, but its value declines to 33 k? at 50°C. At that temperature the R2-R3 divider produces 1.5 V—a balance point at which U2c’s positive, negative, and output terminals are all at 1.5 V, and just about to pull V_RED lower, via D2.

At 70°C, R2 drops to 15.5 k? and the op-amp output drops to 1.0 V, pulling V_RED to about 1.6 V. This action achieves the desired current foldback by limiting the maximum duty cycle at 70°C to 80%. A simple change of resistor values allows the circuit to accept different V_CNTL ranges and to have different temperature- foldback characteristics.