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Equipment designers, particularly those involved with communications and high-end data, face the constant challenges of increasing data rates and greater packaging densities. In turn, these requirements are driving development needs for compact, high-speed components, including connectors.

DESIGN CHALLENGES
High-speed computing and networking system designers have the benefit of choosing from cost-effective, high-speed backplane connectors that utilize edge-coupled and shield-less technology since the introduction of the AirMax VS backplane connector system in 2003. This technology delivers high signal density while exhibiting low insertion loss and crosstalk, allowing systems to scale differential signals up to 12.5 Gbits/s without necessitating a redesign of the basic platform.

Breaking the dependence on metal shields to accomplish consistent high-speed electrical performance also provides design flexibility. Users can allocate individual contacts in a connector module to differential pairs, single-ended signals, or lowlevel power as dictated by system needs. Options for increased column spacing enable more signal traces on a board layer, trading some signal density for lower layer counts and board costs for applications not demanding maximum signal density.

These backplane connectors provide high signal density with connectors configurable for 15 contacts per column and 2-mm column spacing, 63.5 differential pairs, or 190.5 contacts per inch, achievable within a 25-mm card slot pitch. Lowerprofile options provide 12 or nine contacts per column and allow designers to achieve a card slot pitch of 20 mm or less. As systems generate more heat due to increased numbers of processors, additional memory, and higher signal speeds, designers may also employ the lower-profile connectors to minimize obstructions to airflow and significantly improve cooling efficiency.

Even with these connectors, designers now find that density is increasingly critical. The transition from rack-mount servers to denser blade server form factors in the data center is just one example of an industry trend driving the need for more efficient space utilization and improved thermal management. Connector density now extends beyond the traditional measures of the linear density along the edge of the daughtercard or the connector system’s vertical profile.

For connector manufacturers to meet this need, high-speed connector designs must maximize signal density in all three dimensions to address the mechanical and thermal concerns of system designers. Advances to preserve signal integrity at high data rates are necessary to fit more differential signal pairs in a smaller volume.

INCREASING SIGNAL DENSITY
One example addressing density requirements, the ZipLine connector system for backplane and orthogonal midplane applications, initially provides 18 contacts or six differential pairs per wafer on 1.8-mm column spacing. The system also provides 84.6 differential pairs per inch along the card edge.

Adapting the press-fit connectors to a 1.5-mm column pitch can achieve 101.6 signal pairs per linear inch. Line extensions to add connector configurations with nine contacts per signal wafer will enable the connectors’ use in systems with card-slot spacing down to 15 mm.

With the use of edge-coupled technology, increasing the spacing between signal wafers incurs no adverse impact to differential impedance. The larger column spacing may allow users to reduce the number of backplane and daughtercard layers by 50%.

POWER DELIVERY
With more multicore processors and memory, systems require additional power delivery to daughtercards in a chassis. This is addressable either by integrating higher-power contacts in signal connector modules or by installing separate high-power connector modules on the card edge. When a high-speed connector design also provides optional power wafers in a signal module, both signal and power contacts can fit in a single connector.

One such design features a special six-contact power wafer, rated at 6 A per contact with an aggregate capacity to deliver up to 36 A when a power wafer is included in a six-pair module (Fig. 1). Higher power levels are achievable by adding more power wafers, but in doing so, the current-carrying capacity needs to be derated accordingly. The use of a different resin color for the power wafer gives assemblers a visual indicator to differentiate power-signal modules from standard signal modules.

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ORTHOGONAL MIDPLANE ARCHITECTURE
Since the emergence of orthogonal midplane system architecture, more communications equipment designers are adopting this packaging scheme to accomplish direct, efficient connections between multiple line cards and a common switch or communications card (Fig. 2). Vertical daughtercards on one side of a midplane have a direct connection to horizontal add-in cards on the opposite side of the midplane.

Orthogonal midplane headers are installable back-to-back and oriented at 90° to each other. The headers’ signal pins share the same vias in the midplane, providing a direct connection while eliminating the need for connecting traces. Reducing the number of backplane signal traces also reduces design complexity. Some orthogonal midplane interconnects can support differential signaling at up to 20 Gbits/s.

To enable proper registration of opposing signal contacts in the vias, the header design requires a different orientation of its press-fit tails when compared to standard backplane headers where all tails lie along the centerline of each signal wafer. For an orthogonal midplane header, differential signal pair tails are offset to the left and right of the centerline while the differential pairs in adjacent signal wafers are offset by one contact position. The result is a perfect match of signal contacts, ground contacts, and plated via holes when two headers are rotated at 90° during back-to-back installation.

In addition to ensuring correct contact registration, connector manufacturers must consider the signal integrity of the link. Most typically employ a combination of electrical simulation and test for optimization and performance validation, which also yields the recommended footprint and printed-circuit board (PCB) layout for the subject connectors. For some orthogonal midplane designs, these recommendations include the use of wide antipads surrounding the vias to minimize impedance mismatch and the positioning of adjacent differential pairs at 90° to minimize crosstalk.

With a six-pair, 12-column connector, a design can include up to 72 differential pair crossovers in a single module. With flexible connectors, designers may also allocate connector columns to backplane or power wafers for product customization.

NEXT STEPS
With growing IP traffic driving demand for aggregate bandwidth, designers continue to test the limits of existing backplane connectors and challenge manufacturers to develop next-gen components. While high-speed serial backplane links in current telecom and datacom equipment typically fall in the range of 2.5 to 6 Gbits/s, designers are aiming to achieve 40 Gbits/s and higher.

To accomplish these goals, designers must balance three components: chip packages, multilayer backplanes and daughtercards, and connectors. Until cost-effective SERDES transceivers become available, the less costly next step may be the use of multiple parallel lanes to achieve higher throughputs. For example, the initial implementation of a 40-Gbit/s Ethernet link might consist of four high-speed serial lanes with each lane operating at 10 Gbits/s.

Obviously, designers continue to demand faster data links with high signal density in small packages, which the market already provides. But even the latest technologies will continue to evolve, driven by the need for ever greater speeds and density.