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In surveying customers, Cadence found four key challenges facing designers of IC packages and systems-in-package (SiPs). Ambitiously, the company seeks to address them all in its SPB 16.2 release of the Allegro printed-circuit board (PCB) and IC packaging/SiP flows, which delivers advanced IC package/SiP miniaturization, design cycle reduction, and DFM-driven (design for manufacturing) design, along with a new power integrity modeling capability.

The first challenge is the inexorable onrush of high-density interconnects (HDIs) on PCBs. As flip-chip and BGA packages move to smaller and smaller pin pitches to accommodate silicon fabricated at 65 nm and below, there’s no avoiding HDIs. In the SPB 16.2 Allegro release, Cadence has implemented a constraint-driven and automated environment for HDI design.

The flow creates correct-by-construction HDI via structures. In addition, it gives users feedback during the design process about what their HDI structures actually will look like. As a result, users can spend more time doing design work as opposed to concerning themselves with manufacturing rules. A second concern is increasing design-team productivity in the face of closing market windows for consumer electronics. To this end, the SPB 16.2 release facilitates team-based design partitioning and collaboration.

“You can take an IC package, cut it up into as many pieces as you like, and have that many designers work on it all at once,” says Keith Felton, Cadence’s group director of product marketing for IC package/SiP and front-end logic authoring technologies.

“We let you split designs in two ways,” he continues. “One is like slicing a cake or pie, where you get the whole slice from top to bottom, or you can split it up by layers. This is very effective for HDI. One designer can have layers one through three, and another layers four through six, each working on their own via structures.”

The partitioning can also be used to better balance resources among team members. “Design team members usually have particular skills,” Felton points out. “One member might be good at breakouts for flip chips, while another might be good at designing power networks. You can break out the design in a way that lets you take advantage of people’s strengths.”

Third on the list of designer concerns is the relationship between design and manufacturing for IC packages and SiPs. “Wire bonding is a big issue here,” says Felton. With more designers stacking die and connecting them to substrates with wirebonds, manufacturing shops are often finding the wirebond jobs problematic at best.

Thanks to a joint marketing partnership between Cadence and Kulicke and Soffa, a manufacturer of wirebonding equipment, the Allegro flow now takes in validated 3D wire-profile libraries that allow designers to determine during the design process whether their proposed wirebond scheme will cause any problems in manufacturing. “If a user is trying to do something that cannot be manufactured given the wire profile he’s chosen, the tool will alert him. Then he can try another wire profile until he gets to one that is certified as bondable,” explains Felton.

Last but not least among IC package and SiP design concerns is the powerdelivery network (PDN). The PDN must provide sufficient power to the die while doing so in an efficient manner, and also provide it in a stable fashion. The network’s impedance profile must meet the design’s needs and minimize the voltage-ripple effects of simultaneous switching on the die.

The SPB 16.2 release endeavors to build in the ability to design PDNs correctly from the start, as opposed to post-design verification approaches that lead to engineering change orders and respins. It will be available in the fourth quarter. Contact Cadence directly for pricing information.

CadenCe design systems • www.cadence.com