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Logic design at the gate or module level for discrete implementations has effectively gone away, with the exception of buffers and analog designs. The move to micros has turned much of today’s system design into large chips and software. Custom logic is still needed, but it often resides in ASICs, complex programmable logic devices (CPLDs), and FPGAs.

ASICs aren’t a bad choice if you have gobs of money and time, along with an engineering team. But if you need a less ambitious and possibly more flexible solution, then CPLDs and FPGAs are your likely choices. Development tools for these platforms as well as the need to delve into hardware definition languages (HDLs) like Verilog or VHDL, though, often turned determined developers away to other, more familiar tools.

This has changed with improvements in FPGA integrated development environments (IDEs), especially in simplifying the development process and in integration with evaluation and development kits (Fig. 1). Now, developers can turn out FPGA and CPLD designs in days using low-cost platforms like Avnet’s $39 Xilinx Spartan-3A kit (Fig. 2).

Almost any digital design can be churned out in an FPGA, with greater flexibility than discretes and low-density chips. Rewiring is a matter of dragging a logical wire in an IDE, recompiling a design, and downloading it to the target device. One-time programming versions of many CPLDs and FPGAs are available, but most development platforms are reprogrammable.

FPGAs won’t be turning into power chips, but analog designers now have more choice when it comes to dynamic designs. Actel’s Fusion family combines digital FPGA logic with a range of analog inputs and outputs. The family doesn’t always eliminate the need for off-chip analog circuitry, but it can make for a single-chip solution for many applications.

BOARD OR CHIP
FPGA and CPLD designs often are completed in isolation since the tools can handle only these devices, but they eventually wind up on a circuit board. Altium Designer (see “System Design Environment Goes Soft” , ED Online 18334) is an IDE that looks to span chips and circuit boards. It can handle FPGA logic design as well as printed-circuit board (PCB) design at the same time. It even can manage designs with multiple FPGAs or FPGAs from different vendors.

Not to be overlooked is the FPGA’s ability to handle hard-core and soft-core processors (see “FPGAs Pushing MCUs As The Platform Of Choice,” ED Online 19149). Tiny cores like Lattice Semiconductor’s Mico8 or the Xilinx PicoBlaze fit into small FPGAs, and multicore solutions are occurring more often. Standard cores like ARM’s Cortex-M1 or Freescale’s ColdFire can be found in Altera’s FPGAs.

Incorporating processor cores into a design has changed the way designers see FPGAs. Adding custom IP to an FPGA is common, but building systems using only standard IP around standard processor cores is a valid approach as well. This method is very interesting to application programmers who would not know a logic gate if it fell off their mouse. The use of standard components to create a programmable module eliminates much of the complexity of FPGA design. Programmers can thenconcentrate on the software for their custom platform.

PROGRAMMED LOGIC
Another take on custom systems is to use microcontrollers as black boxes. In times past, this would be frowned upon because of cost and a board real-estate point of view, but times are changing. Several factors are pushing this change.

First is the complexity of interfaces. Where once a buffer and some simple logic were required, a microcontroller now sits between a serial interface and a USB interface or an Ethernet interface. There is a wide variety of very low-cost, low-power microcontroller chips that can be easily programmed for dedicated functions that are as small as 2 by 3 mm like Microchip’s PIC10 (Fig. 3).

Of course, the advantage is that a single class of chips can be programmed for a range of applications, from motor control to remote-control input. The main problem is a lack of communication standards between controllers with the exception of higher-end controller-areanetwork (CAN) devices.

So, where is that next FPGA-based IFD coming from?