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An age-old truism in the system design realm is that the software is always ready to be checked out before first ASIC silicon is in hand. This leaves the members of the design team with an equally ageold conundrum: How are they to verify their first crack at an application stack and associated drivers without hardware to run them on? Waiting until that first silicon comes from the fab is an uncomfortable and often untenable option.

The answer, of course, is prototyping with FPGAs, and it has been for some time. Fabricated as they are on advanced silicon processes, today’s FPGAs have more than enough performance to handle running the signal-processing algorithms, the drivers, the operating system (OS), and even applications on top of the OS. There are other ways of approaching this process with more traditional verification methodologies such as simulation and emulation, but they can be too slow for most teams.

Given the capabilities of today’s FPGAs (Altera’s Stratix IV family offers up to 680k logic elements), some design teams may be tempted to design their own prototyping boards. This was common some years back, given that most designers tend to feel, with some justification, that they’re closest to their own design and thus are best equipped to design a prototyping vehicle.

If the ASIC design will indeed fit into one FPGA, it’s probably safe to go this route. But if the design must be partitioned across multiple FPGAs, this is not necessarily a wise route to take. Designing prototyping boards is a full-time endeavor in its own right, and you’re probably better off spending your time debugging the ASIC itself rather than the board you’re trying to design to prototype it.

Consequently, there are a number of commercially available FPGA prototyping products designed for exactly this purpose, often complete with the software required to properly partition your design. Such commercial boards enable systems houses to functionally verify very large ASIC designs of well over 10 million equivalent ASIC gates.

INTERFACING TO REAL-WORLD STIMULUS
For example, GiDEL’s PROCstar III board packs up to four of Altera’s Stratix III FPGAs (Fig. 1). That’s enough capacity to handle pipelined systemon- a-chip (SoC) designs up to 12 million ASIC gates. If that’s not enough for your design, multiple boards can be combined for even greater capacity.

The PROCstar III boards also illustrate another important facility of FPGA boards in the prototyping realm, and that is their ability to handle real-world interfaces for simulation of various kinds of stimulus. Many applications, including wireless and wireline, require designers to feed the prototype with simulated network traffic to evaluate their performance, while other applications must be fed with streaming audio/video for similar purposes. As do many commercially available FPGA boards, the PROCstar III boards accept a variety of plug-in daughterboards for communication protocols such as CameraLink, DVI, and Gigabit Ethernet.

Another prototyping system that exemplifies the performance available in commercial offerings is the latest member of the HAPS family from Synopsys’ Synplicity Business Group. The HAPS-51T is based on Xilinx’s Virtex-5 LX330T FPGAs. Like GiDEL’s product, it’s a suitable prototyping vehicle for applications using high-speed serial interfaces like PCI Express, SATA, and Gigabit Ethernet.

The HAPS-51T takes advantage of the LX330T devices’ 24 RocketIO GTP transceivers and adds on-board DDR2 memory. Furthermore, to achieve an expandable and modular architecture, the board uses what Synopsys calls the HapsTrak high-speed daughterboard connectivity scheme. HapsTrak comprises a set of guidelines for pinouts and mechanical characteristics that help ensure compatibility with earlier and future generations of HAPS motherboards and daughterboards.

Sporting one of the industry’s highest capacities, the DINI Group’s DN7006K10PCIe prototyping system handles up to 15 million equivalent ASIC gates while providing chip-tochip low-voltage differential signal (LVDS) speeds of 1.2 Gbits/s. Based on Altera’s Stratix III FPGAs, the board comes with up to six FPGAs that allow users to run their designs at nearreal- time clock speeds. The FPGAs, which come in 1760-pin packages, provide up to 1120 I/Os per chip. The board packs a host of connectivity features as well as four DDR2 memories. Reference designs, diagnostics, and models for partitioning are included.

One of the more capable lineups in the marketplace is that of EVE, whose family of FPGA-based emulation systems comes complete with a compiler that automatically converts ASIC design constructs into FPGA constructs. This eliminates any need to change the ASIC’s RTL. Users gain full visibility into all signals at runtime without recompiling, enabling quick debugging.

The latest addition to EVE’s line, dubbed ZeBu-Personal, is aimed at block-level verification and the system- integration phase of the design cycle, in which multiple logic blocks and software must be verified together (Fig. 2). Hardware design and software development teams can share the same system and design representation, and they can easily collaborate when debugging complex hardware/ software interactions.

ZeBu-Personal handles up to 5 million ASIC gates and offers up to 512 Mbytes of design memory. Using Xilinx’s Virtex-5 LX330 FPGAs, the system delivers emulation speeds of up to 60 MHz (design clock; system clock runs at 300 MHz). The system permits co-simulation with the industry’s leading RTL simulators (VCS, NC-Sim, and ModelSim) as well as debug with Springsoft’s Verdi debug suite.