Copyright © 2006 Penton Media, Inc., All rights reserved.
Printing of this document is for personal use only.
Reprints

Arm and its partners are looking to give 8- and 16-bit microcontroller vendors fits with its Cortex M0 architecture. This optimized implementation of the Cortex M1 is designed to run on FPGAs. Its small size and lower power will allow it to be coupled with mixed-signal peripherals.

The Cortex M0 is one-third the size of the popular ARM7TDMI- S. The base Cortex M0 configuration requires only 12k gates, which is on the same order as many 8- and 16-bit microcontroller processor cores. Memory and peripherals would be the same size regardless of the core’s width, so the issues in choosing a system will turn more to development tools and developer efficiency.

The Cortex M0 and M1 use the same instruction set that’s a subset of the Cortex M3. It contains only 60 instructions that are culled from the Thumb and Thumb-2 instruction sets found in other Arm processors (see the figure).

The Thumb-2 complement numbers less than half a dozen instructions related to hardware and operating-system support along with the venerable no operation (NOP) instruction. Most application codes will utilize the Thumb instructions, including branching and arithmetic instructions.

The instruction and architecture complement is designed to host C applications, including device drivers and the operating system. It follows the Cortex Microcontroller Software Interface Standard (CMSIS). Migrating applications up or down to or from other Arm platforms is simply a matter of recompiling.

WAKE UP AND SIP THE POWER
Low-power applications where the microprocessor spends most of its time asleep often use 8- and 16-bit solutions. The Cortex M0 handles this very well with its wakeup interrupt controller support plus its inherent 32-bit capability to do more work per instruction in most instances. This allows the on time in a typical on-off cycle to be smaller— hence, using less power.

The Cortex M0 draws on 80 µW/MHz. Its performance is 0.9 MIPS/MHz. This combination makes it an ideal platform for wireless sensors running protocols like Bluetooth, ZWave, and ZigBee. It also enables designers to bring the computational performance to sensor analysis instead of passing data to a 32- or 64-bit host processor.

The upward compatibility of the Cortex M0 is a definite advantage for developers. Compatibility with the FPGAbased Corex M1 offfers some long-life options since future designs can be moved from a discontinued chip to an FPGA.

Chips based on the Cortex M0 will likely arrive later this year from Cortex M3 vendors such as Atmel, NXP, and Luminary Micro. The Cortex M3 tools from vendors such as Keil and IAR Systems already handle the Cortex M1 and, hence, the Cortex M0.

It has been a couple of years since Luminary Micro hit $1 with its Cortex M3 parts (see “32-Bit ARM MCU Hits One-Dollar Mark” at www.electronicdesign.com, ED Online 12358). The Cortex M0 looks to push pricing to new lows while delivering performance with new highs.

ARM

See Associated Poll