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When most designers think of DFM, they think of deep-submicron SoCs and digital design. But more often, DFM is a factor in analog/mixed-signal flows for RFICs as well. “There’s no such thing as a pure RFIC anymore,” says Marc Peterson, director of RFIC product planning at Agilent EEsof. “All RFICs are mixed-signal chips these days, and they’re moving to the smaller process nodes where process variability is a much bigger problem.”

A key part of mixed-signal design is transistor models, which weren’t always so useful in terms of manufacturability effects such as stress. These parameters have never been part of Berkeley short-channel IGFET (insulatedgate field-effect transistor) models (BSIMs).

Over the past few years, though, transistor models have improved substantially. The Penn State-Philips (PSP) advanced compact model for MOSFETs, released in its first standard version by the Compact Model Council in 2006, accounts for non-quasistatic effects such as electron distribution in the MOSFET channel. PSP models also allow stress-based analysis at the transistor level.

Agilent EESof’s Integrated Circuit Characterization and Analysis Program (IC-CAP) was one of the first transistor modeling tools that implemented the PSP extraction algorithms, enabling foundries to create MOSFET models that included these non-quasistatic effects. “That was important because foundry enablement is critical if you want adoption of a modeling standard,” says Paul Colestock, RFIC marketing lead at Agilent EEsof. “If you can’t capture effects in the model, all the analyses in the world won’t make your silicon correlate.”

Another critical analysis category for mixedsignal design is simulation. “Corner analysis is now done for everything,” says Colestock. “But does that analysis capture everything you want it to? Corner models may or may not include RF effects. Are the models really covering corners for things like maximum oscillating frequency, noise, or intermodulation products? They’re usually not that RF-centric.”

One solution is to run a large number of statistical simulations, but that quickly becomes a bottleneck in the design process. There are ways to achieve decent statistical results without running all of those simulations, though. Agilent EESof’s Golden Gate simulator enables Monte Carlo statistical analysis in a number of ways, including correlation analysis from block to block or over levels of hierarchy. It also offers a full Monte Carlo sampling approach at circuit level.