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Attendees of past Design Automation Conferences (DACs) could count on hearing from EDA vendors and design technologists. This year’s 46th DAC takes a significant step by adding the voices of the tool users themselves. With more than 80 papers focused on the latest in tool use and methodologies, the User Track joins DAC’s technical program when the conference kicks off July 26-31 at the Moscone Center in San Francisco.

The 46th DAC’s technical program comprises a smorgasbord of 54 research paper sessions, featuring 156 talks selected from 733 submissions from around the globe. In the User Track, attendees can hear presentations on a variety of topics such as robust design and test, practical physical design, real-world timing analysis, and front-end power planning and analysis, to name just a few.

A highlight of the conference is sure to come at Monday’s Keynote Panel, in which the CEOs of EDA’s Big Three will chew over their respective visions for the EDA industry’s future. Aart de Geus (Synopsys), Wally Rhines (Mentor Graphics), and Lip- Bu-Tan (Cadence) will take the dais to expound on business and technology issues and to share their respective overall outlooks for EDA. Rhines will return on Thursday to chair a lunch-hour panel session on what “green” means to design automation.

As usual, the DAC program is loaded with opportunities for attendees to learn. The 54 paper sessions are arranged in six parallel tracks that sweep the spectrum of leading-edge EDA technologies. Special session topics include how to prepare for design at 22 nm, designing circuits in the face of uncertainty, verification of large SoCs, bug-tracking in complex designs, and multicore computing.

The 46th DAC program also features panels focused on the hottest issues of the industry, including technical discussions on system prototyping, embedded software design, mixed-signal verification, system-level power challenges, design for manufacturability, and emerging applications of EDA technology.

Finally, six full-day tutorials will be given on Monday and Friday, covering multicore, low-power system-on-a-chip (SoC) design, post-silicon validation and runtime verification, functional verification planning and management, and the challenges of IC design with nanomaterials.

WHAT'S NEW AT THE SYSTEM LEVEL?
High-level synthesis (HLS) continues to be a topic of interest at DAC. Synfora will demo its PICO Extreme Power, a variant of its algorithmic synthesis platform that’s intended to reduce power consumption in mobile devices. PICO Extreme Power is being touted by Synfora as the industry’s first algorithmic synthesis tool to automatically minimize power consumption at the system level based on a variety of techniques, including automatic insertion of multi-level clock gating.

Multi-level clock gating enables clock gating to be applied to a computation block in an application accelerator at any level in the hierarchy. PICO Extreme Power has delivered savings of up to 50% using this technique, a claim backed by results obtained by researchers at Rice University and the Indian Institute of Science.

PICO Extreme Power plays well with Atrenta’s SpyGlass-Power, a tool that delivers accurate RTL power estimates. Designs completed using the two tools in concert showed power reductions of 16% and 53% compared with designs without block-level clock gating.

Speaking of Atrenta, it will continue to expand and refine its focus on early design closure at DAC this year. Whereas conventional flows capture designs at the RTL stage with debug and closure occuring during back-end implementation, Atrenta’s tool suite enables capture of the design at the architectural phase with design closure at RTL.

At DAC, Atrenta will unveil a fully integrated tool suite that allows capture of a design at the specification, or request for quote (RFQ), phase and supports iterative refinement throughout RTL development, resulting in a smooth and predictable handoff to the back-end implementation flow (Fig. 1).

Another HLS stalwart, Forte Design Systems, will display the latest version of its Cynthesizer SystemC HLS software. Cynthesizer 3.6 boasts several new technologies, including SystemC 2.2 support, features for partitioning complex hierarchical systems, control-based design support, memory-handling upgrades, and scalability improvements.

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Cynthesizer lets designers choose either SystemC 2.1v1 or the latest SystemC 2.2 release as their design-entry language. Its design-partitioning feature splits the design into multiple parts while automatically determining data dependency between blocks and creating an appropriate interface. Finally, Cynthesizer v3.6 adds an interface-IP generator for design teams to design and create validated, synthesizable interfaces for use in their design.

Cynthesizer v3.6 comes standard with Forte’s TLM synthesis capability, with pricing starting at $275,000. Cynthesizer’s partitioning and interface-generator features start at $40,000 as an add-on to Cynthesizer.

GET AN EARLY DROP ON POWER
As always, getting a handle on power consumption early in the design process is on most designers’ minds. ChipVision Design Systems has enhanced its PowerOpt tool’s capabilities for systemlevel power optimization and has also incorporated significant improvements in language support for designs written in ANSI C, C++, and SystemC. PowerOpt now performs enhanced loop pipelining with automatic run-out support for automatic pipeline flushing. It provides memory access optimizations and eliminates false paths from designs.

Through generation of an SDC constraint file, PowerOpt enables creation of the lowest-power architectures that can be synthesized to gates using RTL synthesis. The latest version also incorporates enhanced clock-gating optimization to determine lowest-power configuration on a register-by-register basis as well as finite state-machine (FSM) encoding that minimizes switching activity to reduce power. The new version of PowerOpt will be available at the end of this month.

On the virtual platform front, CoWare will show its latest electronic system virtualization technologies and how CoWare delivers an executable specification that serves the entire development cycle. CoWare’s tools produce a processor design and implementation of processor model and RTL that can be seamlessly integrated into CoWare Virtual Platform or into FPGA or RTL simulators. They can speed up the architecture design of SoC platforms through early exploration and efficient performance optimization of the interconnect and memory subsystem using ARM AMBA-based virtual platforms.

In the CoWare flow, software development, integration, and test are accomplished through a fully virtualized ARM reference design virtual platform running Google’s Android where the developers can benefit from advanced debugging and software analysis capabilities delivered through Eclipse-based development tools. Lastly, the flow is augmented by processor, interconnect, and peripheral model support representing IP from ARM, MIPS, Renesas, IBM, Tensilica, Toshiba, VeriSilicon, Sonics, and Rambus.

MOVING DOWN IN THE FLOW
In the mainstream design and verification portions of the flow, DAC will showcase a large number of new product and technology introductions. Here are some of the highlights to look for on the show floor and demo suites.

FishTail Design Automation has worked with Texas Instruments to create new technology and a flow for the automated generation of merged-mode design constraints. This work, and its application to a 2 million cell-instance design with more than 30 clocks and 30 operational modes, will be presented in a User Track paper called “The Automated Generation of Merged-Mode Design Constraints.”

The work described in the joint Texas Instruments-FishTail paper at DAC describes the flow, in which a front-end IP design team provides FishTail’s Focus tool a spreadsheet that captures how input ports and configuration registers are programmed in each of the modes (Fig. 2). This mode-table spreadsheet, along with the RTL and clock definitions for the design, are used to automatically generate a super-mode constraint file that correctly constrains the design for a range of operating modes. This flow is applicable for front-end design teams designing new IP blocks.

Satin IP Technologies will be showing its VIP Lane product, which works within customers’ design flows to turn users’ design practices for building IP blocks or whole SoCs into a robust set of quality criteria. VIP Lane automates the implementation and documentation of design quality metrics at no extra cost in engineering time or resources, the company claims.

RTL designers are just as power-conscious these days, if not more so, than the system architect working at higher levels of abstraction. To that end, Sequence Design’s PowerArtist-XP combines power analysis and automatic power reduction all within an integrated environment.

The RTL designer, without having to be a power expert, can analyze, monitor, and reduce power consumption in a design from 10% to 50% or more within hours on unfamiliar multi-million instance blocks. A powerful graphical user interface aids power management, enabling the RTL designer to quickly understand where, when, and why power is consumed as well as what precise changes should be made to reduce it.

In other power-analysis-related news, Apache Design Solutions will be showing its Totem, an integrated power- and noiseintegrity platform that addresses the challenges associated with global couplings of power/ground noise, substrate noise, and package/printed-circuit board (PCB) capacitive and inductive noise. Aimed at analog, mixed-signal, memory, and high-speed I/O designs, Totem incorporates transistor-level noise injection, parasitics extraction, package modeling, dynamic analysis, and design debug in a single-flow environment.

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ON THE VERIFICATION FRONT
Continuing its drive to make hardware-assisted verification available to the masses, EVE will launch ZeBu-Server, a scalable emulation system capable of handling up to 1 billion ASIC gates. Priced at less than a penny per gate for large configurations, ZeBu-Server offers a high level of automation, short compile time, multi-user capabilities, and fast execution speeds.

ZeBu-Server suits all SoC verification needs across the entire development cycle, from hardware verification and hardware/ software integration to embedded software validation. It can be used as a multi-user, multi-mode accelerator/emulator with a typical performance of 10 MHz on a 40 million-gate design. Included with the hardware is a compiler with multicore capability to break the linearity of the compile time on large designs.

ZeBu-Server offers automated, fast, and incremental compilation from SystemVerilog, Verilog, and VHDL RTL code. As an interactive hardware/software debugging tool, ZeBu-Server includes complete RTL signal dumping and support for SystemVerilog Assertions. ZeBu-Server is shipping now and is priced from $150,000.

Formal verification is another technology that’s growing in popularity, especially as the number of functional modes in portable devices rises. At DAC, Jasper Design Automation is announcing a technology it calls QuietTrace, which brings advanced visualization technology for RTL development. It also delivers enhanced behavioral analysis, with multiple RTL revision comparison supporting incremental design.

Jasper will also demonstrate its ProofGrid technology, which is available in its forthcoming JasperCore product as well as in the JasperGold verification environment. ProofGrid technology efficiently delivers formal proof power for multiple proofs, multiple tasks, multiple users, multiple applications, and multiple computers, even across multiple business units, Jasper says. It also represents core engine enhancements for faster proofs and lower memory consumption, leading to higher proof capacity.

In the functional verification arena, Real Intent will be at DAC to showcase its latest technology in its Ascent, Meridian, and PureTime family of products. Ascent, an early functional verification (EFV) tool, has been upgraded with enhanced static linting capabilities and additional path-based formal analysis capabilities, such as X-propagation verification to ensure safe X handling in the design utilizing automatic formal techniques.

Meridian CDC, which performs clock-domain-crossings (CDC) verification, now can perform hierarchical analysis and verify designs with free-running clocks. PureTime, a timing-exception verification tool, now offers enhanced design-constraint checking capabilities. Together with timing exception verification, designers can improve the quality of design constraints.

OneSpin Solutions will demonstrate a new root cause analysis framework that eases and speeds property and design debugging, increasing formal assertion-based verification (ABV) productivity. OneSpin’s formal ABV technology helps design, verification, and integration engineers to significantly accelerate a wide range of RTL verification tasks. OneSpin will present two ongoing inbooth tutorials, one designed for formal ABV newcomers to get started, and one for experienced users to take formal ABV to the next productivity and quality level.

GateRocket will show a new version of its RocketDrive FPGA verification and debug platform for Altera’s Stratix IV line, along with updated RocketVision software featuring dynamic block selection, on-the-fly scope selection, and full mixed Verilog/ VHDL support. Both are now available.

Analog/mixed-signal designers still rely on Spice, with many turning to fast-Spice variants. Berkeley Design Automation will demo the latest release of its Analog FastSpice (AFS) unified circuit verification platform. In addition to the speed boost that fast-Spice users are accustomed to, the 2009_05 release of AFS includes upgraded matrix solvers that deliver efficient convergence and fast transient analysis for pre-layout and post-layout circuits with up to 10 million elements. Also, a multicore capability delivers a further performance gain.

If you’re a Spice user, you probably will want to check out Altos Design Automation’s Liberate MX, an ultra-fast, generalpurpose library characterizer for memories and custom macro blocks. The new tool generates instance-specific library models in Liberty format including advanced current source models for timing and noise (CCS and ECSM).

Unlike traditional block characterization approaches that perform partitioning based on circuit topology, Liberate MX’s use of dynamic partitioning lets it account for effects common at advanced process nodes such as interconnect coupling and transistor stress. Liberate MX does not rely on circuit pattern matching and hence can be used for a very wide range of circuit types from complex lower-power SRAMs with power gating to custom blocks such as serializers-deserializers (SERDES).

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ANALOG MODELING ADVANCES
From Lynguent comes the ModLyng Event Driven Mixed- Signal Toolkit (EDMS), a collection of libraries containing building blocks that support the creation of models for analog devices using event-driven (digital) techniques. Models created using the ModLyng EDMS Toolkit simulate orders of magnitude faster than analog models of the same device, the company claims.

The ModLyng EDMS Toolkit is used with Lynguent’s Mod- Lyng, an integrated modeling environment that enables users to create, manage, and support HDL-based simulation models for analog, digital, and mixed-signal domains by graphically assembling mathematical, functional, and behavioral building blocks into the model’s topology.

IP reuse will be a key topic in the technical program at DAC this year; it also will be the subject of product and technology launches. Arteris, a provider of network-on-chip (NoC) interconnect technology, is showcasing a product called P-NoC that now enables the company to address all requirements for SoC interconnect including the top-level interconnect, block-level interconnect, peripheral interconnect, and interchip links.

The P-NoC interconnect product is optimized for connectivity of peripheral IP cores such as USB, infrared interfaces, control communications, audio, touchscreen, and others. The product also offers an efficient means of communicating to IP core register interfaces. Available now, P-NoC pricing starts at just over $100,000.

Many design teams are taking a holistic approach to chip, package, and board design in efforts to better control signal integrity. To that end, Sigrity is introducing next-generation technology for package model extraction with XtractIM Version 3.0, which will e available for production use in early July.

Rather than simply creating package models for further analysis, XtractIM users can quickly determine if the package design meets the performance requirements of the targeted chip. The software visually displays impedance and coupling along the length of signal nets in a way that enables package engineers to instantly pinpoint performance issues even in complex designs.

WHAT'S NEW IN IMPLEMENATIONS?
Getting to timing closure is one of the biggest obstacles to taping out an SoC design. With that in mind, Magma Design Automation’s Talus 1.1 RTL-to-GDSII chip implementation system leverages Magma’s unified data model to perform timing optimization concurrently during routing.

Included with the release is the Talus Flow Manager, which includes out-of-the-box reference flows for RTL-to-GDSII, multi- VDD, low-power design and high-performance design; engineers can easily tune the reference flows for specific applications. Also new to Talus is the Visual Volcano, an analysis environment and integrated information display that allows an engineer to quickly track many parameters of the design, including run times, timing, power, and area (Fig. 3).

At DAC, Pyxis Technology will demonstrate its NexusRoute- HPC, a custom design routing technology built to support the needs of today’s digital and analog custom designers. The NexusRoute- HPC reduces design time from weeks to hours by providing highly automated hierarchical custom routing and an integrated “what-if” analysis capability. Pyxis will also show its NexusRoute-SOC, an SoC digital routing technology optimized for advanced technologies at 45 nm and below.

Of further interest to full-custom analog layout designers is Tanner EDA’s schematic-driven router, which brings enhanced layout productivity. The router, which complements the company’s integrated schematic-driven layout (SDL) tool and layout device generator (DevGen), is an automatic routing engine integrated directly into SDL. It speeds layout by automatically routing non-critical nets while allowing the designer to focus on routes that truly require expensive hand craftsmanship.

RTL SYNTHESIS SEES GAINS
Potentially one of the most interesting DAC launches comes from Oasys Design Systems, which will unveil its RealTime Designer, a physical RTL synthesis tool for designs of up to 100 million gates. The tool can take such large designs from RTL to placed gates in a single pass and in a fraction of the time taken by traditional synthesis, Oasys says. RealTime Designer’s RTL placement approach limits synthesis-layout iterations.

RealTime Designer follows a “place-first” methodology that partitions the RTL into blocks, places the RTL in the context of a floorplan, and implements each block all the way to placement. Chip-level constraints are automatically propagated across the blocks, and the design is optimized for the best possible quality of results. Further, the tool automates the process of checking the design for congestion and other layout issues. At completion, RealTime Designer produces a placed design and a netlist that meets the constraints in the context of the desired floorplan.

Attempts to migrate designs to smaller process geometries below 90 nm are often plagued by unexpected process variation effects. Among the more pernicious of these are well-proximity effects, which can play havoc with MOSFET electrical characteristics. Typically, designers try to anticipate these issues and deal with them through heuristics-based guardbanding, but this can extract a toll in area. Or, they can iterate through a series of postlayout extracted netlists. In this case, the penalty is time.

Solido Design Automation will demonstrate its Solve Well Proximity application, which is intended for use with the company’s Variation Designer tool. The combination deals with wellproximity effects by leveraging foundry-provided parameters that are included in the Spice model files but are not normally used due to the lack of appropriate tools at the circuit design stage.

Chip designers can use the application during the circuit design stage to proactively account for well-proximity effects. Designers can determine which devices are sensitive to proximity effects and by how much. They also can obtain the appropriate proximity parameter values and minimum well distances. These values are back-annotated into the schematic and are then used by the layout engineer, reducing the silicon area occupied by excessive guardbanding and eliminating iterative post-layout simulations.