================================================= EDA Alert e-Newsletter PlanetEE - www.planetee.com Electronic Design - www.elecdesign.com March 1, 2005 ================================================= Today's Table of Contents: 1. Viewpoint Exclusive -- Consider ASIPs As An ASIC Alternative 2. Pact Smooths Design Of Planes, Trains, And Automobiles 3. ASIC Verification Platform Targets Multimedia Applications 4. Tool Migrates P-CAD PCB Designs To Cadstar Format 5. Tensilica Joins EDA Consortium 6. Happenings - Design Automation and Test in Europe (DATE 2005) - IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2005) - 2005 EDA Tech Forum (sponsored by Mentor Graphics) - IEEE International Symposium on Quality of Electronic Design (ISQED 2005)
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************ Webcast: Advances in Mixed Signal Testing Wednesday, March 9, 2005 -- 2:00 pm EST Sponsored by: LeCroy
With the explosive growth in the use of microcontrollers, engineers who design or test products in fields ranging from computers to automotive electronics need to test and debug products that include both analog signals and multiple digital lines. This seminar will present new technology that allows engineers to add 32 digital channels to their existing four-channel oscilloscopes. It will also present easy-to-use techniques for testing a mixture of analog and digital signals in this environment. Emphasis will be on practical examples including setup, triggering, decoding of digital buses, and making measurements on a mixture of analog and digital signals.
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Embedded designers have a host of constraints to deal with such as low power consumption, high performance, and reliability. Products and trends addressing these issues can be seen in our Embedded Systems Conference ShowCast, where tiny, low-power 8-bit MCUs will be side-by-side with the latest boards utilizing high-speed interconnects such as PCI Express. The ShowCast will also highlight topics such as hardware-based security, increased use of high-capacity mobile storage, enhanced software-development tools and operating systems plus the latest in COTS.
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Designing and deploying ASICs is becoming a prohibitively expensive and risky endeavor. While there are many silicon implementation alternatives that may replace ASICs, application-specific instruction processors (ASIPs) can provide a flexible solution because they offer high performance and shorter design times.
Opportunity exists for ASIPs to flourish, but there's a barrier to their widespread adoption: the inability to program them efficiently. Solving that problem involves developing a more productive ASIP programming methodology that sacrifices little system performance.
Two major converging trends are contributing to a discontinuity in traditional IC design and deployment. First, there's more cost, risk, and unpredictability associated with ASIC design. The cost of designing an ASIC has risen over 250-fold during the past five process generations. More expensive EDA tools and mask-set costs can largely take the blame for that. Despite the sizable NRE costs, there is no guarantee of a first-generation design meeting its functional specification. In fact, 30% to 40% of ASIC first spins do not work. There are many reasons for this: Deep-submicron (DSM) effects introduce more uncertainty in transistor behavior; designs have grown exponentially in terms of gate count (Moore's Law); and the increasing heterogeneity of on-chip components. ASIC design is costly and unpredictable today, and this will only intensify in future process generations.
The second major trend is that time-to-market -- or time-to-money -- windows for many silicon implementations have shrunk dramatically. We are in the "consumer era" for ICs -- that is, devices like cellular telephones, digital cameras, portable audio players, printers, and network equipment are driving the semiconductor market. These information appliances have ever-changing application and market requirements.
The combination of these two trends is dramatic: More complex ASIC designs must be readied in less time.
A new implementation medium for system functionality is required. The answer may be programmable silicon that has the potential to replace ASICs in many system implementations. Programmable silicon refers to any part where software plays a seminal role in its functionality. Types of programmable silicon include:
-- General-purpose processors (GPPs): programmable processors for general-purpose computing -- Co-processors: hardwired, possibly configurable parts with a limited programming interface -- FPGAs: devices that can be reprogrammed at the gate level -- ASIPs: instruction-set processors specialized for a particular application domain
When employing any of these alternatives for system implementation, designers are tasked with programming the device -- providing a program that results in the combined hardware/software system implementing the desired application. This program could be single-threaded machine code, values for control registers, configuration bits, or multiprocessor multi-threaded machine code. By using an off-the-shelf prepackaged part, these programmable silicon solutions overcome the increasing cost and risk of designing ASICs.
As you might expect, each programmable silicon alternative has advantages and disadvantages. When comparing performance, flexibility, design time, and power, ASIPs offer:
-- Performance: By having hardware for efficient execution of key computational kernels, ASIPs can support many applications at a high performance level. -- Flexibility: With software being a major part of the system, ASIPs can easily adapt to changing applications and market requirements -- Design time: Designing software can be much faster and less costly than designing hardware of equivalent functionality -- Power: ASIP power dissipation is not prohibitively high like FPGA power dissipation is for many applications.
The shift from ASICs to ASIPs has happened in some domains -- signal processing and graphics, most notably. However, the major barrier to ASIP adoption is the difficulty in programming them. Most ASIPs lack tool support for efficiently synthesizing (or compiling) high-level language source code, but that is rapidly changing as the EDA community develops solutions to tackle the programming problem.
One such example is DSP design. Designers develop and analyze algorithms using floating-point models in Matlab from The Mathworks, and then manually convert them to fixed-point versions in an implementation language such as C or Verilog. This numeric conversion process and manual design re-coding is time-consuming, error-prone, and inhibits designer productivity.
Recent technology advances have made Matlab a true implementation environment through the use of analysis and automation, which includes moving algorithms from floating-point to fixed-point representations and shortening algorithm validation with simulation acceleration. Such technology reduces the time from algorithm creation to deployment on target fixed-point DSPs, as well as offers an automated path from concept to implementation.
While trends suggest a move away from ASICs, they will play an ongoing role in electronics for many more process generations to come. Newer and more flexible processors are on the horizon as are tools for ASIP design, offering design teams higher performance, more flexibility and power, and shorter design times.
Contact Niraj Shah at: mailto:niraj@catalyticinc.com
To comment on this Viewpoint, go to Reader Comments at the foot of the Web page: EDA Alert ==> http://nls.planetee.com/t?ctl=3B9B:F3222
******* 2. News ******* Pact Smooths Design Of Planes, Trains, And Automobiles
A streamlined design process to meet the emerging needs of complex electromechanical platforms, such as automobiles, airplanes, and trains, is the goal of a pact between Mentor Graphics and UGS, a provider of product lifecycle management (PLM) software and services. The companies pledged to deliver tight interoperability between their products beginning in the second half of 2005.
Enhancements will be made to UGS's Teamcenter product-knowledge management and lifecycle collaboration platform and its NX digital design and analysis package. Teamcenter will provide the integrated design of an electromechanical product together with the overall system design. NX provides an environment for conducting associative electrical routing through an integrated design environment.
Meanwhile, Mentor will enhance its Capital Harness System (CHS), a design flow for system capture, integration, and analysis in the context of the platform and subsequent engineering of associated harnesses, to provide tight interoperability between the electrical and mechanical worlds. The collaboration will also enable more efficient management of the change process throughout the entire electromechanical product lifecycle.
ASICs for multimedia systems bring complex verification challenges, and ProDesign's CHIPit Gold Edition Pro verification platform brings a full range of capabilities to bear on the task. Uses range from the initial phases of design algorithm creation, through the basic IP development and debugging, to the validation of complex SoC designs and early "quasi prototyping" for firmware and software development. The platform will be demonstrated at next week's DATE 2005 in Munich (booth E4100).
The standalone system communicates with the host via ProDesign's 528-Mbit UMRBus communication system or via a 100-Mbit Ethernet interface. The system supports the newest interfaces, such as DVI Input and Output, LVDS, PCI Express, and USB 2.0. It uses two Xilinx Virtex-II Pro XC2VP70/100 FPGAs in the largest pin-count package, offering multi-gigabit serial links, embedded PowerPC processors, and 744 user I/Os on six extension sites. The system also comes with a comprehensive software package that includes CHIPit Manager, Visibility Tool, HDL Bridge and Signal Tracker.
The CHIPit Gold Edition Pro platform is available beginning in the second quarter of 2005. Per platform, U.S. pricing starts at $29,000, and European pricing starts at 23,000 Euros.
******* 4. News ******* Tool Migrates P-CAD PCB Designs To Cadstar Format
Concerns often arise for PCB designers when it comes to the preservation of legacy design files and loss of investment in those earlier designs. To address those issues, Zuken USA and its technology partner, LogicSwap, launched a migration tool that allows users of P-CAD to transfer PCB design data, schematic databases, and libraries to Zuken's Cadstar, a Windows-based PCB design suite. In addition to this complete new solution, users will be able to convert back to P-CAD, if required, using the Cadstar to P-CAD solution.
Additional migration solutions are available for OrCAD Capture and Layout, GenCAD Support, Gerber file recovery, and bidirectional EDIF support for schematic databases. Currently, LogicSwap is developing migration tools from Protel and PADS to Cadstar.
LogicSwap's P-CAD to Cadstar Module, available now, is priced from $3000.
Zuken USA ==> http://nls.planetee.com/t?ctl=3B9F:F3222 LogicSwap ==> http://nls.planetee.com/t?ctl=3BA6:F3222
Tensilica Inc., a vendor of configurable processors and, more recently, tools to create these processors, has joined the EDA Consortium. Tensilica's XPRES (Xtensa PRocessor Extension Synthesis) Compiler, launched last summer, enables the rapid development of optimized SoC devices while sparing designers the need to hand code their hardware in HDLs. The EDA Consortium, an industry-wide coalition of some 100 companies, is charged with promoting the EDA industry's health and raising awareness of EDA's role in the global economy.
************** 6. Happenings ************** Design Automation and Test in Europe (DATE 2005) ICM Messe, Munich, Germany March 7-11, 2005 http://nls.planetee.com/t?ctl=3BA2:F3222
IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2005) Schapiro Building, Columbia University, New York, N.Y. March 14-16, 2005 http://nls.planetee.com/t?ctl=3BA0:F3222
2005 EDA Tech Forum (sponsored by Mentor Graphics) Hilton Hotel, Long Beach, Calif. March 16, 2005 (first in a worldwide series of 18 events; see website for other dates and locations) http://nls.planetee.com/t?ctl=3BA4:F3222
IEEE International Symposium on Quality of Electronic Design (ISQED 2005) Doubletree Hotel, San Jose, Calif. March 28-30, 2005 http://nls.planetee.com/t?ctl=3BA9:F3222
Advertising/Sponsorship Opportunities: Bill Baumann mailto:bbaumann@penton.com
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