Shyam Sunder Tiwari is a managing director with Sensors Technology Private Ltd., Gwalior, India. He holds an MSc in physics from the University of Agra, India, and a PhD in physics from the University of Bombay, India. Email address: sst@sensorstechnology.com
8 results found for Shyam Sunder Tiwari, displaying items 1 - 8
April 23, 2009[Ideas For Design] Sensor Signal Converter Outputs Both NPN And PNP Signals
Matching a sensor interface with a programmable logic converter or controller hardware that can accept only one type of input—npn or pnp—can be difficult. The last-stage modification circuit described here solves this problem. Designers can use it to convert an npn input to a pnp type or incorporate it in the last stage of the sensor design to generate both npn and pnp outputs. The npn and pnp transistors used in the circuit should be highcurrent- gain (hfe >...
March 12, 2009[Ideas For Design] Low-Power Logic Gate Protects Fluid Sensor From Leakage Current
Fluid-level sensing is very common in industrial applications and now is being used in domestic applications to sense water levels in overhead tanks. The greatest challenge for designers is to make these sensors operate with ultra-low power using battery voltages between 2 and 6 V, while making the device insensitive to potential damage from leakage current coming from mains power running pumps and valves. The design described here uses three sections of a...
February 12, 2009[Ideas For Design] Power Control Circuit Limits On Time To Prevent MOSFET Burnout
A power control device that protects against MOSFET burnout was designed using a well-known gated-oscillator circuit. The circuit prevents excessive On time for the MOSFETs beyond a permitted limit. The R1-C1 time constant forms a timing circuit that limits the On-time pulse period and automatically generates its own maximum permitted On/Off duty cycle (Fig. 1). Without this timing circuit, if the input...
November 17, 2008[Ideas For Design] Superior JFET Biasing Improves Amplifier Performance
An N-channel JFET has a low bias current when its gate is biased negative to the source. However, this requires either that the gate voltage be biased negative with respect to the source voltage or that source voltage be biased positive with respect to the gate voltage. For ac amplifier designs, gate biasing can be made self-biased by using an RC network at the source to hold the positive voltage for a period longer than the time period of the input pulse/frequency...
