Mark Miller is the vice president of marketing and business development of Design-for-Manufacturing (DFM) at Cadence Design Systems Inc., San Jose, Calif. Email address: markmill@cadence.com Web site: http://www.cadence.com
3 results found for Mark Miller, displaying items 1 - 3
January 23, 2006
[Web Exclusive] Physical Verification in the Age of One Billion Transistors, One Thousand Design Rules, and Million Dollar Mask Sets
Physical-verification cycle time increases significantly with each new process generation. Rule-deck complexity contributes considerably to this effect. The number of design rules grows rapidly as manufacturers push the limits of their lithographic processes to print feature sizes smaller than the wavelength of light. New rules approximate the complex, model-based, optical-proximity-correction (OPC) algorithms...
January 20, 2005[Design View / Design Solution] Nanometer Yield Enhancement Begins In The Design Phase
In moving to nanometer process technologies at 130 nm and below, semiconductor designers face a variety of physical and electrical effects that can significantly degrade circuit performance. For these nanometer designs, traditional corrections applied after tapeout are simply ineffective, requiring more broadly based development strategies. With nanometer processes, silicon success depends on the designer's ability to anticipate manufacturing concerns before tapeout. To achieve...
January 20, 2005[Design View / Design Solution] Power Analysis Plays Key Sign-Off Role
For large designs using nanometer technologies, power and signal-integrity (SI) problems loom as a subtle cause of failed silicon. The impact of IR drop alone can be substantial: In signal and clock nets, a 10% IR drop can result in a 50% variation in timing. At the same time, increased parasitic effects in nanometer designs give rise to noise-related timing problems-and silicon failures for designs that seem to pass conventional sign-off methods. To avoid these problems, companies like...
