John Sanguinetti is co-founder and chief technical officer of Forte Design Systems. He was the principal architect of VCS, the Verilog Compiled Simulator, and was a major contributor to the Verilog’s resurgence in the design community. He has 15 publications and one patent. Also, he wrote the Verilog Online Training course. He holds a PhD in computer and communication sciences from the University of Michigan, 1977.
1 results found for John Sanguinetti, displaying items 1 - 1
January 12, 2006[Technology Report] The Rise Of Transaction-Level Modeling
After many years of expectation, we're finally seeing increased use of generally usable methods of hardware design at an abstraction level higher than RTL. This is more than just behavioral level, as it's been known for a long time. Levels of abstraction are commonly seen as being implemented by translating a language at one level into a language at a lower level, e.g., Verilog RTL to Verilog netlist. However, there's another way to implement a level of abstraction, and that's via...
