David Stringfellow, staff design consultant with Synopsys Professional Services, has led or contributed to the development of several SoCs in applications ranging from automotive engine controllers to x86 processors. He holds four U.S. patents, was named a General Motors Fellow in 1991, and is a Synopsys Distinguished Author. Stringfellow received a BS and MS in electrical and computer engineering from Purdue University. Web site: http://www.synopsys.com
2 results found for David Stringfellow, displaying items 1 - 2
October 25, 2007[Design View / Design Solution] Practical Ways To Estimate, Implement, And Verify SoC Decoupling Capacitance
Deep-submicron systems-on-a-chip (SoCs) require a power-grid voltage drop of much less than 10% of VDD. Decoupling capacitors, or decaps, help achieve this goal by minimizing switching noise. Determining the amount of decap required for an SoC involves many considerations, but the task needn't be a chore. The approach described in this article allows you to allocate decap accurately and with minimal area overhead for deep-submicron (DSM) SoCs. This...
January 19, 2006[Design View / Design Solution] Rail-Signoff Analysis Ensures SoC Power Integrity
More than ever, power integrity is vital in the successful creation of today's system-on-a-chip (SoC) designs. That's because e xcessive rail voltage drop ( IR drop) and ground bounce can create timing problems. Also, excessive current can cause electromigration and related thermal effects, leading to chip failures. The first steps designers must take to prevent these problems are solid power-network planning and implementation. The next step is a good rail-signoff analysis flow to...
