Mohit Bhatnagar is currently responsible for marketing digital prototyping and physical synthesis products for Cadence Design Systems Inc., San Jose, Calif. He holds a PhD in electrical engineering from North Carolina State University, Raleigh. Web site: http://www.cadence.com
2 results found for Mohit Bhatnagar, displaying items 1 - 2
July 6, 2006[Design View / Design Solution] Glossary
Clock gating: Switching off the clock to flip-flops if the transition during clocking results in the same value. Dynamic Voltage Frequency Scaling (DVFS): Change both the voltage and frequency of a logical block during operation based on the task it performs to produce a cubic power reduction. Isolation cells: Prevent physical damage to sections of the IC that interface to power switch-off modules. ...
July 6, 2006[Design View / Design Solution] Save Those Watts With A Power-Aware Design Flow For SoCs
At a time when a single data center may consume more power than millions of homes1, it's easy to see that power consumption has become critically important for all designs—not just battery-powered products. Leakage power now dominates 90- and 65-nm devices, and high power consumption imposes ever more severe heat and performance penalties. Of course, the chip-or system-level power requirements are in addition to the perennial requirements of higher performance,...
