Jack Erickson is a product marketing director for RTL synthesis at Cadence Design Systems Inc., San Jose, Calif. He holds a BSEE from Tufts University, Medford, Mass. Web site: http://www.cadence.com
3 results found for Jack Erickson, displaying items 1 - 3
September 26, 2007
[Design View / Design Solution] Bringing Physical Predictability To Logic Design
Historically, wireload models have been inadequate for accurate modeling of wire delays. Furthermore, the inaccuracy worsens with each new process generation. Logic designers see one timing representation of their design, and physical designers see something entirely different. This discontinuity impacts the success of the project in several ways.
July 6, 2006[Design View / Design Solution] Glossary
Clock gating: Switching off the clock to flip-flops if the transition during clocking results in the same value. Dynamic Voltage Frequency Scaling (DVFS): Change both the voltage and frequency of a logical block during operation based on the task it performs to produce a cubic power reduction. Isolation cells: Prevent physical damage to sections of the IC that interface to power switch-off modules. ...
July 6, 2006[Design View / Design Solution] Save Those Watts With A Power-Aware Design Flow For SoCs
At a time when a single data center may consume more power than millions of homes1, it's easy to see that power consumption has become critically important for all designs—not just battery-powered products. Leakage power now dominates 90- and 65-nm devices, and high power consumption imposes ever more severe heat and performance penalties. Of course, the chip-or system-level power requirements are in addition to the perennial requirements of higher performance,...
