Author - Jeff Boyer

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Jeff Boyer	Write for Electronic Design
Jeff Boyer, design-for-test engineer for Intel in Austin, Texas, holds both a BS and an MS in electrical engineering from Texas A&M University, College Station. Email address: jeff.boyer@intel.com
1 results found for Jeff Boyer, displaying items 1 - 1

October 26, 2006 [Design View / Design Solution]
Reducing The Design Impact Of DFT In The Nanometer Era
Design-for-test (DFT) is essential to ensure that complex designs can be thoroughly tested. Testing demands continue to increase as designs grow in gate count and fabrication process technologies evolve. Fortunately, advances in DFT techniques have avoided major design requirements and restrictions for test. In fact, some approaches have reduced the impact of test on designs. Structured DFT techniques are commonplace due to their high fault coverage and support...