Author - Naresh Baliga

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Naresh Baliga	Write for Electronic Design
Naresh Baliga is the vice president of marketing at Inapac Technology Inc. He holds an MBA from the Wharton School of Business and an undergraduate degree in electrical engineering from the Indian Institute of Technology, Delhi. Email address: nbaliga@inapac.com
1 results found for Naresh Baliga, displaying items 1 - 1

May 24, 2007 [POV: Point Of View]
Die Stacking Solves The Mobile Device Memory Crunch
The rapid adoption of media-rich applications in portable consumer products is requiring progressively higher memory speeds and capacities, especially for volatile memory that stores data during operation, as in DRAM. The economics of system-on-a-chip (SoC) design and manufacturing are challenging engineers to find new architectural approaches to embedding large blocks of DRAM in a single chip. One attractive path leads off the Moore's Law treadmill to system-in-package (SiP)...