Graham Allan joined the Solutions Group at Synopsys as Senior Manager, Memory IP, in June 2007. A veteran of DRAM and memory design, he holds 15 patents, has spoken at several industry conferences, and has contributed to the SDRAM and DDR standards at JEDEC since 1992, including holding a chairmanship position from 1996 to 1999. Email address: designwareip@synopsys.com Web site: http://www.synopsys.com
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August 14, 2008
[Web Exclusive] A Summary Of The DDR Memory Controller Standard—Wait, There Isn’t One!
The number of SoCs that require an interface to off-chip memory is increasing. As a result, more and more designers are turning to DDR SDRAM interfaces such as DDR, DDR2, and DDR3 to address their low-cost, security of supply, storage capacity, and performance requirements. Fortunately for those designers, DRAMs have been standardized since the 1970s. But this still leaves a challenge that most SoC engineers don’t recognize until things start to go wrong.
