Vipin Tiwari currently serves as Virage Logic’s senior product marketing manager for advanced technology nodes, responsible for advanced product definitions and product planning. He joined the company in 2000 as a design engineer and then later served as a design manager with a focus on the company’s low power non-volatile memory (NVM) products. Before joining Virage Logic, Mr. Tiwari served as a design engineer and team leader for ST Microelectronics in India, working on chip level floor planning, place and route, and SRAM design. He holds four U.S. patents and currently has two patents pending. Mr. Tiwari has a Bachelors degree in Technology, Electronics Engineering, from ITBHU, India and an MBA degree from Santa Clara University, Calif. Web site: http://www.viragelogic.com
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June 29, 2009
[POV: Point Of View] Should Dual Rail Go Mainstream in Deep Nanometer Era?
Deep sub-nanometer designs are stressed with large process variability. SRAM-bits have the most aggressive design rules in the SoCs, and the most variability. A dual rail solution offsets some of the variability at the cost of additional design efforts. Dual rail solutions appear to be complex, but several area, power, and performance tradeoffs can be made to simplify the design.
