861 results found for David Maliniak, displaying items 1 - 20
November 5, 2009[TechView: EDA] Parasitic Extraction Tool Targets Next-Generation Custom ICs
Achieving design closure in a system-on-a-chip (SoC) development project generally requires a great deal of patience. SoCs tend to include more and more custom circuitry, which means long simulation runs and some stabs in the dark at something resembling signoff. The combination of more transistors and the need to model more complex parasitic effects can double, if not quadruple, the runtimes of circuit-level simulation. One way to get...
October 29, 2009
[TechView: EDA] Synopsys Jumps Into ESL-Synthesis Pool
There’s a new entry in the ESL synthesis marketplace in the form of the Synopsys Synphony high-level synthesis (HLS) tool, which the company has aimed directly at the heart of the burgeoning HLS market. Synphony is intended to synthesize algorithms written in the MathWorks’ Matlab language into optimized RTL for ASICs, FPGAs, prototyping, and software development work.
October 20, 2009
[TechView: Test] Scope Delivers High Signal Fidelity To 20 GHz
As the performance levels of embedded systems escalate, the tools required to verify and debug them must keep pace. Most designers need to examine analog and digital signals simultaneously, with many dealing with memory buses in terms of integrity and timing. Combining the probing attributes of a high-performance logic analyzer with the analog capabilities of a real-time scope, the MSO70000 series is Tektronix’s take on a mixed-signal scope that’s up to the challenge.
October 22, 2009[Engineering Essentials] Pick The Right Probe And Get The Most Out Of It
The first rule of thumb to be observed in choosing a test probe involves the probe’s bandwidth. “The bandwidth of the probe needs to be three to five times the signal bandwidth,” explains Jae-Yong Chang, Agilent Technologies’ product manager for probes. “Customers often are confused by signal bandwidth, which is driven by the fastest rise time of your circuitry.” When it comes to using high-end active test probes, it’s important to remember that these devices are...
October 22, 2009[Engineering Essentials] High-End Probes Actively Improve Test Results
A steady stream of advances has elevated test and measurement instruments to the point where they can reveal minute details of signals with lightning-quick rise and fall times. So, then, what about test probes? The last thing test engineers want or need is a probe that’s going to influence their measurements or fail to deliver the full bandwidth that’s available to them on the scope. Fortunately, today’s high-end probes are constructed to sidestep these...
September 30, 2009
[TechView: Test] Signal Analyzers Cover Both Ends Of The (Cost) Spectrum
Adding to the high and low ends of its spectrum-analyzer family at the same time, Agilent has covered the bases with the launches of its N9000A CXA low-cost analyzers and its N9030A PXA high-end instrument. In both cases, as in all members of the company’s X series signal analyzers, the instruments are consistent in terms of their measurement framework and their ability to enable design teams to grow with them.
September 23, 2009
[TechView: Test] Spectrum Analyzer Delivers Unprecedented Ku-Band Performance
The Tektronix RSA6120A spectrum analyzer incorporates a feature set that targets digital-RF designers working in the Ku-band frequencies (12 to 18 GHz). It offers extremely high spurious-free dynamic range of 75 dB in the Ku-band, an enhanced set of radar measurements, and switched-filter preselection that overcomes the limitations of earlier spectrum analyzers.
September 24, 2009[Technology Report] Tool Up For The FPGA Blitz
FPGA usage divides into two primary segments. Historically, the foremost role of FPGAs has been to verify an ASIC, system-on-achip (SoC), or application-specific standard part (ASSP). Designers now will use FPGAs to prototype a portion or all of their design, to tweak the same, or as a platform to get ahead on developing system software. According to some industry experts, as many as 90% to 100% of ASICs today are prototyped on FPGAs. For many years, a main...
July 23, 2009[Leapfrog: First Look] In Adding Control-Logic Support, A High-Level Synthesis Tool Goes Full Chip
High-level synthesis (HLS), or the notion of synthesizing a design into RTL from a higher level of abstraction, has been gaining currency among design teams. For some time now, there have been compelling reasons to explore HLS methodologies for certain kinds of designs, or certain blocks within a larger design, such as signal- processing blocks. Such a design flow can get you to RTL faster from languages like C++ or SystemC. And because simulation at the transaction...
July 23, 2009[Technology Report] 46th DAC Is This July’s San Francisco Treat
Attendees of past Design Automation Conferences (DACs) could count on hearing from EDA vendors and design technologists. This year’s 46th DAC takes a significant step by adding the voices of the tool users themselves. With more than 80 papers focused on the latest in tool use and methodologies, the User Track joins DAC’s technical program when the conference kicks off July 26-31 at the Moscone Center in San Francisco. The 46th DAC’s technical program comprises...
June 25, 2009
[TechView: EDA] Accellera-SPIRIT Consortium Merger Boosts EDA Standards Efforts
Hoping to prove that two isn’t necessarily better than one, the EDA standards bodies Accellera and the SPIRIT Consortium have agreed to combine into a single organization. The combined entity, which will go forward as Accellera (with IP standards branded as SPIRIT IP-XACT), will seek to exploit synergies, and possible new opportunities, in the development of design and verification language-based and IP standards.
June 25, 2009[Leapfrog: First Look] Tool Automates Power Optimization Of Embedded SoC Memories
System-on-a-chip (SoC) design teams have long labored to optimize their creations for power, but doing so in the memory portions of the devices has lagged behind. Today’s memory-IP (intellectual property) providers build complex power-management schemes into their products, yet the design of the control logic to take maximum advantage of these schemes is daunting. Attempts to get a handle on dynamic power consumption using sleep modes are...
June 18, 2009[Technology Report] Test Instruments Stay Ahead Of The Curve
Maintaining one’s competitive edge in this economic downturn often comes down to the tools used to get the job done. In terms of test instruments, this is especially true. Without oscilloscopes, spectrum analyzers, and other instruments with the speed and bandwidth to capture today’s high-speed serial bus traffic, it’s virtually impossible to verify the performance of many systems. On top of that, the same instruments are essential to...
June 18, 2009[Technology Report] EDA Remains The Enabler Of Much-Needed Innovation
Some years ago, the electronic design Automation consortium (edAc) adopted the phrase â??where electronics Beginsâ?? as a tagline. coined by richard Goering during his EE Times days, the phrase remains more than apt for edA. As silicon integration grew more complex over the past three decades, the automation of otherwise manual and labor-intensive phases of the design cycle became ever more critical. one could scarcely imagine todayâ??s ...
June 11, 2009[TechView: EDA] Software Confronts New Yield-Management Paradigm
Yield analysis, a science formerly left to process engineers in foundries, is not a luxury any longer. According to Collett International’s research, at least 40% of designs face at least one respin with an associated delay of from four to six weeks. At least 22% of designs will see two respins, so make that delay 12 to 16 weeks. Some 60% of the issues causing these respins are silicon related. Let’s not forget that the new mask sets for each respin...
June 11, 2009[Engineering Feature] The Mixed-Signal Angle On DFM
When most designers think of DFM, they think of deep-submicron SoCs and digital design. But more often, DFM is a factor in analog/mixed-signal flows for RFICs as well. “There’s no such thing as a pure RFIC anymore,” says Marc Peterson, director of RFIC product planning at Agilent EEsof. “All RFICs are mixed-signal chips these days, and they’re moving to the smaller process nodes where process variability is a much bigger problem.” A key part of mixed-signal...
June 11, 2009[Engineering Feature] Design For Manufacturing Sheds The Hype
Four to five years ago, the hype surrounding design-for-manufacturing (DFM) technology for advanced system-on-a-chip (SoC) design was near insufferable. At that time, 90 nm was the state-ofthe- art process node and most fabless houses were preparing for a shrink down from the 130-nm node. And without some way of feeding process parameters back into the design side, the likelihood of any chip yielding at 90 nm was slim to none. This set off a bit of panic among the...
April 30, 2009
[Web Exclusive] PCI eXtensions for Instrumentation (PXI) 101
PCI eXtensions for Instrumentation (PXI) is a rugged PC-based platform that offers a high-performance, low-cost means of deploying measurement and automation systems.
April 28, 2009
[Web Exclusive] Timing Jitter 101
In any system that uses voltage transitions to represent timing information, jitter is an unfortunate part of the equation. In essence, jitter is the deviation of timing edges from their intended locations.
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