850 results found for David Maliniak, displaying items 1 - 20
June 25, 2009
[TechView: EDA] Accellera-SPIRIT Consortium Merger Boosts EDA Standards Efforts
Hoping to prove that two isn’t necessarily better than one, the EDA standards bodies Accellera and the SPIRIT Consortium have agreed to combine into a single organization. The combined entity, which will go forward as Accellera (with IP standards branded as SPIRIT IP-XACT), will seek to exploit synergies, and possible new opportunities, in the development of design and verification language-based and IP standards.
June 25, 2009[Leapfrog: First Look] Tool Automates Power Optimization Of Embedded SoC Memories
System-on-a-chip (SoC) design teams have long labored to optimize their creations for power, but doing so in the memory portions of the devices has lagged behind. Today’s memory-IP (intellectual property) providers build complex power-management schemes into their products, yet the design of the control logic to take maximum advantage of these schemes is daunting. Attempts to get a handle on dynamic power consumption using sleep modes are...
June 18, 2009[Technology Report] Test Instruments Stay Ahead Of The Curve
Maintaining one’s competitive edge in this economic downturn often comes down to the tools used to get the job done. In terms of test instruments, this is especially true. Without oscilloscopes, spectrum analyzers, and other instruments with the speed and bandwidth to capture today’s high-speed serial bus traffic, it’s virtually impossible to verify the performance of many systems. On top of that, the same instruments are essential to...
June 18, 2009[Technology Report] EDA Remains The Enabler Of Much-Needed Innovation
Some years ago, the electronic design Automation consortium (edAc) adopted the phrase â??where electronics Beginsâ?? as a tagline. coined by richard Goering during his EE Times days, the phrase remains more than apt for edA. As silicon integration grew more complex over the past three decades, the automation of otherwise manual and labor-intensive phases of the design cycle became ever more critical. one could scarcely imagine todayâ??s ...
June 11, 2009[TechView: EDA] Software Confronts New Yield-Management Paradigm
Yield analysis, a science formerly left to process engineers in foundries, is not a luxury any longer. According to Collett International’s research, at least 40% of designs face at least one respin with an associated delay of from four to six weeks. At least 22% of designs will see two respins, so make that delay 12 to 16 weeks. Some 60% of the issues causing these respins are silicon related. Let’s not forget that the new mask sets for each respin...
June 11, 2009[Engineering Feature] The Mixed-Signal Angle On DFM
When most designers think of DFM, they think of deep-submicron SoCs and digital design. But more often, DFM is a factor in analog/mixed-signal flows for RFICs as well. “There’s no such thing as a pure RFIC anymore,” says Marc Peterson, director of RFIC product planning at Agilent EEsof. “All RFICs are mixed-signal chips these days, and they’re moving to the smaller process nodes where process variability is a much bigger problem.” A key part of mixed-signal...
June 11, 2009[Engineering Feature] Design For Manufacturing Sheds The Hype
Four to five years ago, the hype surrounding design-for-manufacturing (DFM) technology for advanced system-on-a-chip (SoC) design was near insufferable. At that time, 90 nm was the state-ofthe- art process node and most fabless houses were preparing for a shrink down from the 130-nm node. And without some way of feeding process parameters back into the design side, the likelihood of any chip yielding at 90 nm was slim to none. This set off a bit of panic among the...
April 30, 2009
[Web Exclusive] PCI eXtensions for Instrumentation (PXI) 101
PCI eXtensions for Instrumentation (PXI) is a rugged PC-based platform that offers a high-performance, low-cost means of deploying measurement and automation systems.
April 28, 2009
[Web Exclusive] Timing Jitter 101
In any system that uses voltage transitions to represent timing information, jitter is an unfortunate part of the equation. In essence, jitter is the deviation of timing edges from their intended locations.
April 27, 2009
[Web Exclusive] Intelligent Testbench 101
Functional verification of large SoC/ASIC designs has always been a catch-22 situation. How does the verification engineer decide that enough simulations have been run on a functional block or full chip? When has he or she thrown enough test vectors at the design to be confident that sufficient coverage has been achieved?
April 24, 2009
[Web Exclusive] Electronic System Level (or ESL) 101
ESL refers to design activity at the electronic-system level, a way of defining SoC system architecture at a relatively high level of abstraction.
April 23, 2009[Technology Report] Wireless-Enabled Systems Challenge Analog/Mixed-Signal Flows
FFrom its inception, the holy grail for the design automation industry has been in the analog realm. Digital logic, with its relatively straightforward structures and topologies, has long been the chief beneficiary of the EDA industry’s efforts. Yet compared to the digital domain, automation of analog and mixed-signal design remains lacking. There are some obvious factors at work. Chief among them is the painstakingly hands-on, custom nature of analog design work. ...
April 23, 2009[Technology Report] The MEMS Wrinkle
One RFIC maker with an interesting set of EDA challenges is WiSpry, which relies on RF-MEMS (microelectromechanical systems) technology to create its chips, components, and modules. The issues a design house faces in incorporating MEMS technology is one that more companies will face as MEMS make their way into a growing array of consumer electronics. There would be no Nintendo Wii game system without them. “We have the classic problem of having two separate tool chains to...
April 20, 2009
[TechView: EDA] IC Development Platform Integrates Proven Tools, Best Practices
Who’s got time to cobble together design flows from various vendors? Synopsys now offers the Lynx all-inclusive design system. And if the notion of procuring a design flow from a single vendor appeals, the Lynx Design System has some compelling points in its favor. At the heart of the Lynx Design System is Synopsys’ production design flow, which rests on a foundation of best practices and recommended methodologies for the best ways to drive tools such as Design Compiler.
March 26, 2009
[TechView: EDA] Try Easing Into Adoption of Formal Verification
Adopters of formal verification have reaped benefits from their efforts. Those who have taken the plunge report that assertion-based verification translates into gains in productivity and quality. But formal verification requires quite a bit of know-how to really take advantage of it. The lack of that know-how has stymied a lot of would-be adopters over the years. To ease the path, OneSpin Solutions has come up with a step-by-step approach to comprehensive assertion-based formal verification.
March 19, 2009
[TechView: Test] Comprehensive Test Suite Eases Transition To DDR3 Memory Architectures
To address the needs relative to DDR3 design and integration, Agilent is offering a comprehensive DDR3 protocol test package that will span probes and slot interposers, a high-speed logic analysis module, and compliance and analysis software tools. At the center of the offering is the 16962A logic analysis module, billed as the industry’s fastest with support for state speeds up to 2 Gtransfers/second. Timing speed is specified as up to 8 GHz (quarter channel; up to 400 Msamples deep).
March 12, 2009[Leapfrog: First Look] Software Takes Guesswork Out Of PCB Power Integrity
It’s never been more important than in the current economic climate to get products to market with development costs held as low as possible. One of the ways that systems manufacturers can achieve that goal is through power analysis. After all, it wasn’t that long ago when all ICs ran on 5 V. But since then, we’ve seen voltage requirements spiral down to as low as 0.9 V. Complicating these matters even further, many ICs have multiple voltage ...
March 4, 2009
[TechView: EDA] Rapid-Prototyping Platform Pulls Together Hardware, Software, And IP
So on the heels of its acquisitions of HARDI Electronics and Synplicity, Synopsys has forged a rapid-prototyping flow that patches the holes in the ad-hoc debugging methodologies that have been cobbled together across the industry. Dubbed Confirma, the platform includes implementation and debug software; high-performance prototyping boards and systems; a transaction-based co-verification methodology; and intellectual-property (IP) and services offerings.
February 24, 2009
[Product Report] Inline Error-Injection Tool Stress-Tests PCI Express Links
Along with this proliferation of PCI Express technology comes an increased need for tools with which to verify compliance to the standard. Even though a given device may be compliant, that device’s behavior will vary depending on the implementation, and even with the operating system and drivers associated with it for that matter. Handling this kind of testing in a deterministic manner is becoming more difficult over time.
Email address: 
prev. page
[1]
