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Author Articles

  • TEST

    By Taher Abbasi, November 24, 2008

  • blank

    By Taher Abbasi, April 08, 2008

  • Go Abstract To Speed Up Your Design Flow

    By Taher Abbasi, August 19, 2002

    New silicon-process-technology nodes are coming out every 18 months. Each process node brings a doubling of chip gate capacity. On top of that, the new 90-nm technology with 7.2-ps gate delays and 10 layers of interconnect offers the capacity to...

  • Symbol Test

    By Taher Abbasi, June 15, 1996

    This is a test to display how ASCII symbols get trashed when multiple edits are made to an article through the Admin tool