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Ron Press

Ron Press is the technical marketing manager of the Silicon Test Solutions products at Mentor Graphics Corp. A 25-year veteran of the test and DFT industry, he has presented seminars on DFT and test throughout the world. He also has published dozens of papers in the field of test. He is a member of the International Test Conference (ITC) Steering Committee and a Golden Core member of the IEEE Computer Society. He holds patents on reduced pin-count testing and glitch-free clock switching. And, he earned a BSEE from the University of Massachusetts.


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Author Articles

  • What’s The Difference Between JTAG (IEEE 1149.1) And IJTAG (IEEE P1687)?

    What’s The Difference Between JTAG (IEEE 1149.1) And IJTAG (IEEE P1687)?

    By Martin Keim, May 18, 2012

    This article details the differences between the older JTAG (IEEE-1149.1) standard and the newer Internal JTAG (IJTAG, IEEE-P1687) standard for test of printed-circuit boards and ICs.

  • Understanding Cell-Aware ATPG And User-Defined Fault Models

    Understanding Cell-Aware ATPG And User-Defined Fault Models

    By Ron Press, February 23, 2012

    ATPG targets faults at IC-gate boundaries, but 50% of defects are located within cells. Learn how cell-aware ATPG and user-defined fault models help to ferret out these hard-to-squash bugs.

  • Reducing The Design Impact Of DFT In The Nanometer Era

    By Jeff Boyer, October 26, 2006

    Design-for-test (DFT) is essential to ensure that complex designs can be thoroughly tested. Testing demands continue to increase as designs grow in gate count and fabrication process technologies evolve. Fortunately, advances in DFT techniques

  • Design-For-Test The Smart Way: dFT With A "Big T" And A "Little d"

    By Ron Press, February 03, 2005

    Design-for-test, or DFT, should facilitate high-quality test, not change the design. Test techniques and strategies need to supply a high-quality test that screens out defective devices, avoiding their shipment to customers. Any change to the design, or

  • Leading-Edge Diagnostic Tools Help Ramp Up SoC Production

    By Ron Press, November 10, 2003

    There’s a direct relationship between the quickest route to volume IC production and profitability. That said, today’s system-on-a-chip (SoC) designs demand more elaborate testing and application of more types of tests...