Mark Miller

Mark Miller is the vice president of marketing and business development of Design-for-Manufacturing (DFM) at Cadence Design Systems Inc., San Jose, Calif.

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Physical Verification in the Age of One Billion Transistors, One Thousand Design Rules, and Million Dollar Mask Sets

By Mark Miller, January 23, 2006

Physical-verification cycle time increases significantly with each new process generation. Rule-deck complexity contributes considerably to this effect. The number of design rules grows rapidly as manufacturers push the limits of their lithographic proces
Nanometer Yield Enhancement Begins In The Design Phase

By Mark Miller, January 20, 2005

In moving to nanometer process technologies at 130 nm and below, semiconductor designers face a variety of physical and electrical effects that can significantly degrade circuit performance. For these nanometer designs, traditional corrections applied aft
Power Analysis Plays Key Sign-Off Role

By Mark Miller, January 20, 2005

For large designs using nanometer technologies, power and signal-integrity (SI) problems loom as a subtle cause of failed silicon. The impact of IR drop alone can be substantial: In signal and clock nets, a 10% IR drop can result in a 50% variation in tim

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Mark Miller

Author Articles

Physical Verification in the Age of One Billion Transistors, One Thousand Design Rules, and Million Dollar Mask Sets

Nanometer Yield Enhancement Begins In The Design Phase

Power Analysis Plays Key Sign-Off Role