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Anand Iyer

Anand Iyer is the product marketing director for the Encounter digital IC design platform at Cadence Design Systems Inc., San Jose, Calif. He holds an MBA from Santa Clara University, Calif., an MSEE from the University of California, Santa Barbara, and a master's of technology in reliability engineering from IIT, Bombay, India.


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  • Glossary

    By Pete McCrorie, July 06, 2006

    Clock gating: Switching off the clock to flip-flops if the transition during clocking results in the same value. Dynamic Voltage Frequency Scaling (DVFS): Change both the voltage and frequency of a logical block during operation based

  • Save Those Watts With A Power-Aware Design Flow For SoCs

    By Pete McCrorie, July 06, 2006

    At a time when a single data center may consume more power than millions of homes1, it's easy to see that power consumption has become critically important for all designs—not just battery-powered products. Leakage power now dominates 90- and 65-