392 results found for TechView: EDA, displaying items 1 - 20
June 25, 2009
Accellera-SPIRIT Consortium Merger Boosts EDA Standards Efforts
Hoping to prove that two isn’t necessarily better than one, the EDA standards bodies Accellera and the SPIRIT Consortium have agreed to combine into a single organization. The combined entity, which will go forward as Accellera (with IP standards branded as SPIRIT IP-XACT), will seek to exploit synergies, and possible new opportunities, in the development of design and verification language-based and IP standards.
—
David Maliniak
June 11, 2009 Software Confronts New Yield-Management Paradigm
Yield analysis, a science formerly left to process engineers in foundries, is not a luxury any longer. According to Collett International’s research, at least 40% of designs face at least one respin with an associated delay of from four to six weeks. At least 22% of designs will see two respins, so make that delay 12 to 16 weeks. Some 60% of the issues causing these respins are silicon related. Let’s not forget that the new mask sets for each respin...
—
David Maliniak
April 20, 2009
IC Development Platform Integrates Proven Tools, Best Practices
Who’s got time to cobble together design flows from various vendors? Synopsys now offers the Lynx all-inclusive design system. And if the notion of procuring a design flow from a single vendor appeals, the Lynx Design System has some compelling points in its favor. At the heart of the Lynx Design System is Synopsys’ production design flow, which rests on a foundation of best practices and recommended methodologies for the best ways to drive tools such as Design Compiler.
—
David Maliniak
March 26, 2009
Try Easing Into Adoption of Formal Verification
Adopters of formal verification have reaped benefits from their efforts. Those who have taken the plunge report that assertion-based verification translates into gains in productivity and quality. But formal verification requires quite a bit of know-how to really take advantage of it. The lack of that know-how has stymied a lot of would-be adopters over the years. To ease the path, OneSpin Solutions has come up with a step-by-step approach to comprehensive assertion-based formal verification.
—
David Maliniak
March 4, 2009
Rapid-Prototyping Platform Pulls Together Hardware, Software, And IP
So on the heels of its acquisitions of HARDI Electronics and Synplicity, Synopsys has forged a rapid-prototyping flow that patches the holes in the ad-hoc debugging methodologies that have been cobbled together across the industry. Dubbed Confirma, the platform includes implementation and debug software; high-performance prototyping boards and systems; a transaction-based co-verification methodology; and intellectual-property (IP) and services offerings.
—
David Maliniak
November 17, 2008 Custom Sources Light Way To 22-nm IC Lithography
Concern is rising about the ability of today’s microlithography equipment to scale below 45-nm design rules and still print with acceptable fidelity. There are different schools of thought on how best to meet this challenge—some more hardwarecentric, others more software-centric, and still others combining elements of both. Thus, there has been a spate of announcements of late in this arena (see “IBM And Mentor Graphics Team Up On 22-nm Computational ...
—
David Maliniak
October 9, 2008 Synopsys Takes The Analog/Mixed-Signal Plunge
Recognizing an opportunity to capture the hearts and minds of the expanding analog/mixed-signal (A/M-S) design community, Synopsys has launched the Galaxy Custom Designer, which takes the Galaxy design platform into the realm of fullcustom design implementation. Custom Designer has been built from scratch in an effort to carve market share from Cadence’s aging Virtuoso analog design environment. Given the push for greater integration in IC...
—
David Maliniak
September 25, 2008 Tools Take On IC-Package And SiP Design Challenges
In surveying customers, Cadence found four key challenges facing designers of IC packages and systems-in-package (SiPs). Ambitiously, the company seeks to address them all in its SPB 16.2 release of the Allegro printed-circuit board (PCB) and IC packaging/SiP flows, which delivers advanced IC package/SiP miniaturization, design cycle reduction, and DFM-driven (design for manufacturing) design, along with a new power integrity modeling...
—
David Maliniak
August 14, 2008 Model Extractor For CMOS Sports Improved RF/DC Parameters
It’s very difficult to create accurate device-simulation models for advanced CMOS digital processes. Why? Because hard-to-model effects like gate accumulation and tunneling, trap-assisted tunneling, and halo effects have become so prevalent at ultra-deep-submicron technology nodes. For designers of RFcapable systems-on-a-chip (SoCs), this has become a critical issue in the accurate prediction of the behavior of highly nonlinear RF circuits,...
—
David Maliniak
June 24, 2008
Formal Verification Suite Takes In Wider View Of Designs
If there’s ever been a knock on formal verification, it’s the amount of time it takes to do a formal run on a full design. Formal tools can only take in so much design data at a given time, forcing design teams to partition the design for formal analysis. Sure, it’ll find bugs that can’t be found any other way, but it can take quite a while to accomplish. In the latest revision of its flagship tool, JasperGold, Jasper Design Automation has made...
—
David Maliniak
May 8, 2008 Try-Before-You-Buy IP Distribution Program Segues Into Implementation
As FPGAs become an increasingly popular implementation platform, their complexity rises accordingly, thanks largely to the proliferation of processor and peripheral IP. A study done by Synplicity last fall found that one-third of all designs implemented on FPGA these days carries at least some IP. With so many designers implementing IP on FPGAs, it would be useful if they had a vehicle through which they can acquire, evaluate, and...
—
David Maliniak
April 24, 2008 Design Flow Halves Development Time For Mixed-Technology PCBs
Once found chiefly in the military and aerospace domains, printed-circuit boards (PCBs) with a mélange of analog, digital, and RF circuitry are now everywhere. In fact, the wireless telecom and consumer sectors are embracing them wholeheartedly. But that doesn’t mean they’ve gotten any easier to design. Mixed-technology PCBs are only growing in density and complexity, encompassing more layers than ever, multiple power domains, and greater sensitivity...
—
David Maliniak
April 10, 2008 Low-Power Methodology Guide Goes Online
Capturing thousands of hours of real-world design experience, a downloadable handbook is available to guide designers in applying the Common Power Format (CPF). The guide draws from the formatâ??s usage by many of the 26 members of the Power Forward Initiative to offer detailed examples of optimized lowpower design using CPF, one of two competing low-power design intent formats (see â??Power-Intent Standards Vie For Designersâ?? Loyalties,â?? Feb. 14, 2008, p. 45, ED...
—
David Maliniak
March 13, 2008 System Design Environment Goes "Soft"
Enabling system design in the “soft” domain, before a hardware platform has been settled upon, brings numerous advantages—not the least of which is maximizing flexibility as deeply as possible into the design process. An important byproduct of such an approach is the ability to create differentiation. To this end, Altium’s Innovation Station comprises a complete system-design environment that combines the company’s Altium Designer software...
—
David Maliniak
December 13, 2007 Power Comes To The Fore In FPGA Design Environment
Power is a chief concern for chip designers, and those who implement their circuitry on FPGAs are no exception. Pressure is mounting to follow the crowd toward low power, but FPGA designers need comprehensive design flows geared toward achieving their power-budget goals. Actel has stepped up with version 8.1 of its Libero Integrated Development Environment (IDE), which combines a pushbutton design flow and GUI wizards with power-driven layout...
—
David Maliniak
December 13, 2007 Function Library Smoothes Path For Matlab-To-C Synthesis
For many design teams, the MathWorksâ?? Matlab language has become the standard for signal-processing algorithm development. Likewise, C is the preferred vehicle for handing off those algorithms to downstream developers. But while Matlab functions are critical for algorithm development, those functions, which are expressed in M-code, have no equivalent Csource code for handoff. Translation of the functions from M-code to C is a time-consuming, manual job. And,...
—
David Maliniak
November 15, 2007 A Pioneering ESL Vendor Readies Its Second-Generation Toolset
Now that an electronic system-level (ESL) tool vendor is using the term “ESL 2.0,” I can hear the snickering already, especially from the hardcore RTL camp. Is this just some kind of marketing ploy intended to sell more of the same-old? Or is there more than meets the eye? Marketing ploy or not, ESL is to some extent a state of mind. As one of the earlier entrants in the ESL arena, CoWare has been rethinking its approach, especially in light of...
—
David Maliniak
November 15, 2007 Verification Library Ensures Compliance Of OCP Interconnects
Virtual platforms used for system-level design are only as good as the models they comprise. Thus, design teams devote considerable time to developing code for verifying these models. But thanks to a system-level verification library for OCP-based (Open Core Protocol) system designs in SystemC, much of the drudgery of this task can be avoided. JEDA Technologies’ OCPchecker verification library comprehensively verifies OCP protocol correctness. The library enforces...
—
David Maliniak
November 5, 2007 Design-For-Test Tool Eliminates Need For Gate-Level Scan
If there's a truism in design debug and test, it's that the earlier you can find a bug, the less costly it is to fix. Thus, finding bugs at RTL is far preferable to finding them after synthesis. With DeFacTo Technologies' HiDFT-Scan, designers can analyze their RTL IC and system-on-a-chip (SoC) designs, create the appropriate scan-test structures, and insert them into the RTL code. HiDFT-Scan works within existing design flows and with...
—
David Maliniak
October 25, 2007 ATPG Tool Meets Growing Demand For Scan Test Compression
As IC design sizes continue to double every 18 to 24 months, those charged with testing the finished product are challenged on multiple fronts. Test-data volume and testing time are expanding, while manufacturing throughput is reduced. The International Technology Roadmap for Semiconductors (ITRS) predicts that by 2008 the industry will need 200 times more test-data volume compression, with the requirement growing exponentially over the next five years. ...
—
David Maliniak
prev. page
[1]
