386 results found for TechView: EDA, displaying items 1 - 20
October 9, 2008 Synopsys Takes The Analog/Mixed-Signal Plunge
Recognizing an opportunity to capture the hearts and minds of the expanding analog/mixed-signal (A/M-S) design community, Synopsys has launched the Galaxy Custom Designer, which takes the Galaxy design platform into the realm of fullcustom design implementation. Custom Designer has been built from scratch in an effort to carve market share from Cadence’s aging Virtuoso analog design environment. Given the push for greater integration in IC...
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David Maliniak
September 25, 2008 Tools Take On IC-Package And SiP Design Challenges
In surveying customers, Cadence found four key challenges facing designers of IC packages and systems-in-package (SiPs). Ambitiously, the company seeks to address them all in its SPB 16.2 release of the Allegro printed-circuit board (PCB) and IC packaging/SiP flows, which delivers advanced IC package/SiP miniaturization, design cycle reduction, and DFM-driven (design for manufacturing) design, along with a new power integrity modeling...
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David Maliniak
August 14, 2008 Model Extractor For CMOS Sports Improved RF/DC Parameters
It’s very difficult to create accurate device-simulation models for advanced CMOS digital processes. Why? Because hard-to-model effects like gate accumulation and tunneling, trap-assisted tunneling, and halo effects have become so prevalent at ultra-deep-submicron technology nodes. For designers of RFcapable systems-on-a-chip (SoCs), this has become a critical issue in the accurate prediction of the behavior of highly nonlinear RF circuits,...
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David Maliniak
June 24, 2008
Formal Verification Suite Takes In Wider View Of Designs
If there’s ever been a knock on formal verification, it’s the amount of time it takes to do a formal run on a full design. Formal tools can only take in so much design data at a given time, forcing design teams to partition the design for formal analysis. Sure, it’ll find bugs that can’t be found any other way, but it can take quite a while to accomplish. In the latest revision of its flagship tool, JasperGold, Jasper Design Automation has made...
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David Maliniak
May 8, 2008 Try-Before-You-Buy IP Distribution Program Segues Into Implementation
As FPGAs become an increasingly popular implementation platform, their complexity rises accordingly, thanks largely to the proliferation of processor and peripheral IP. A study done by Synplicity last fall found that one-third of all designs implemented on FPGA these days carries at least some IP. With so many designers implementing IP on FPGAs, it would be useful if they had a vehicle through which they can acquire, evaluate, and...
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David Maliniak
April 24, 2008 Design Flow Halves Development Time For Mixed-Technology PCBs
Once found chiefly in the military and aerospace domains, printed-circuit boards (PCBs) with a mélange of analog, digital, and RF circuitry are now everywhere. In fact, the wireless telecom and consumer sectors are embracing them wholeheartedly. But that doesn’t mean they’ve gotten any easier to design. Mixed-technology PCBs are only growing in density and complexity, encompassing more layers than ever, multiple power domains, and greater sensitivity...
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David Maliniak
April 10, 2008 Low-Power Methodology Guide Goes Online
Capturing thousands of hours of real-world design experience, a downloadable handbook is available to guide designers in applying the Common Power Format (CPF). The guide draws from the formatâ??s usage by many of the 26 members of the Power Forward Initiative to offer detailed examples of optimized lowpower design using CPF, one of two competing low-power design intent formats (see â??Power-Intent Standards Vie For Designersâ?? Loyalties,â?? Feb. 14, 2008, p. 45, ED...
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David Maliniak
March 13, 2008 System Design Environment Goes "Soft"
Enabling system design in the “soft” domain, before a hardware platform has been settled upon, brings numerous advantages—not the least of which is maximizing flexibility as deeply as possible into the design process. An important byproduct of such an approach is the ability to create differentiation. To this end, Altium’s Innovation Station comprises a complete system-design environment that combines the company’s Altium Designer software...
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David Maliniak
December 13, 2007 Power Comes To The Fore In FPGA Design Environment
Power is a chief concern for chip designers, and those who implement their circuitry on FPGAs are no exception. Pressure is mounting to follow the crowd toward low power, but FPGA designers need comprehensive design flows geared toward achieving their power-budget goals. Actel has stepped up with version 8.1 of its Libero Integrated Development Environment (IDE), which combines a pushbutton design flow and GUI wizards with power-driven layout...
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David Maliniak
December 13, 2007 Function Library Smoothes Path For Matlab-To-C Synthesis
For many design teams, the MathWorksâ?? Matlab language has become the standard for signal-processing algorithm development. Likewise, C is the preferred vehicle for handing off those algorithms to downstream developers. But while Matlab functions are critical for algorithm development, those functions, which are expressed in M-code, have no equivalent Csource code for handoff. Translation of the functions from M-code to C is a time-consuming, manual job. And,...
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David Maliniak
November 15, 2007 A Pioneering ESL Vendor Readies Its Second-Generation Toolset
Now that an electronic system-level (ESL) tool vendor is using the term “ESL 2.0,” I can hear the snickering already, especially from the hardcore RTL camp. Is this just some kind of marketing ploy intended to sell more of the same-old? Or is there more than meets the eye? Marketing ploy or not, ESL is to some extent a state of mind. As one of the earlier entrants in the ESL arena, CoWare has been rethinking its approach, especially in light of...
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David Maliniak
November 15, 2007 Verification Library Ensures Compliance Of OCP Interconnects
Virtual platforms used for system-level design are only as good as the models they comprise. Thus, design teams devote considerable time to developing code for verifying these models. But thanks to a system-level verification library for OCP-based (Open Core Protocol) system designs in SystemC, much of the drudgery of this task can be avoided. JEDA Technologies’ OCPchecker verification library comprehensively verifies OCP protocol correctness. The library enforces...
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David Maliniak
November 5, 2007 Design-For-Test Tool Eliminates Need For Gate-Level Scan
If there's a truism in design debug and test, it's that the earlier you can find a bug, the less costly it is to fix. Thus, finding bugs at RTL is far preferable to finding them after synthesis. With DeFacTo Technologies' HiDFT-Scan, designers can analyze their RTL IC and system-on-a-chip (SoC) designs, create the appropriate scan-test structures, and insert them into the RTL code. HiDFT-Scan works within existing design flows and with...
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David Maliniak
October 25, 2007 ATPG Tool Meets Growing Demand For Scan Test Compression
As IC design sizes continue to double every 18 to 24 months, those charged with testing the finished product are challenged on multiple fronts. Test-data volume and testing time are expanding, while manufacturing throughput is reduced. The International Technology Roadmap for Semiconductors (ITRS) predicts that by 2008 the industry will need 200 times more test-data volume compression, with the requirement growing exponentially over the next five years. ...
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David Maliniak
October 25, 2007 True-3D Chip-Layout Editor Facilitates Stacking Of Disparate Wafers
Say you wanted to create a chip in which a processor fabricated in 32-nm process rules would be combined with memory done on a 65-nm process and analog blocks fabricated at 180 nm. This leads you to consider chip/wafer-stacking technologies, most of which are out of the question for existing layout editors. A favored technique for chip stacking, known as through-silicon via wafer stacking, allows distinct wafers to be stacked on each other and...
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David Maliniak
October 11, 2007 Model Library Supports Virtual Platforms
Not all aspects of electronic-system-level (ESL) design have proved as worthy as others. Yet the virtual platform has seen some of the broadest adoption among ESL technologies. These fully functional software models of complete systems have been in use for several years for the acceleration of system development and hardware/software co-verification. Since its May 2006 acquisition of Virtio, Synopsys has worked to transform that company's virtual-platform offerings from...
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David Maliniak
October 11, 2007 FPGA Synthesis Adroitly Handles Late Incremental Design Changes
FPGA synthesis comes with pitfalls that are becoming more of a liability as the devices themselves grow in complexity. Timing closure can take multiple synthesis iterations. Also, design iterations are getting longer. Last-minute design changes mean a full place-and-route run, requiring hours for a large FPGA. And, it's difficult to control and analyze how logic is mapped to device-specific blocks. Mentor Graphics' Precision RTL Plus tool takes these issues...
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David Maliniak
September 27, 2007 DFM-Aware Yield-Driven Router Boosts Yields As It Speeds Closure
Manufacturability is paramount as IC designers move to process nodes below 90 nm. It's bad enough that tool runtimes are significantly longer and timing closure becomes much more challenging. But then designbased yield limiters, or "gotchas," sap performance and cause yields to plummet. Tied directly to the chip layout itself, these profit killers must be designed out from the start and can't be fixed in the fab. Yet a new generation of...
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David Maliniak
September 27, 2007 Tool Facilitates Hard-IP Quality Risk Assessments; Collaboration Puts Collected Info Online
As the first deliverable in its planned suite of IP-ecosystem tools, the Fabless Semiconductor Association (FSA) has released version 3.0 of its Hard Intellectual Property (IP) Quality Risk Assessment Tool. The tool collects information about an IP vendor, its design methodology, and the IP family under evaluation to develop a risk assessment profile across seven criteria: IP design, integration, verification, process technology, product documentation, ...
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David Maliniak
September 27, 2007 Digital Interface Analysis Kicks Up Spice A Notch
Spice has long been a favored tool for pc-board signal-integrity signoff, but it's always possible to improve on a good thing. To that end, Synopsys and SiSoft have integrated the former's HSpice simulator with the latter's Quantum-SI tool. The combo automates the analysis of entire digital interfaces for both timing and signal integrity. Further, Quantum-SI leverages computer server farms to run HSpice's highaccuracy simulations in parallel, increasing analytical throughput....
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David Maliniak
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