September 16, 2009
The Devil Is In The Details—Bulkhead Wiring Penetration Considerations
It’s often the little things in life that seem to cause the biggest problems, and it’s no different in design engineering. That small detail, that one piece of the puzzle that was overlooked or underappreciated, can cause the largest project to grind to a halt, resulting in missed deadlines, expensive rush charges and contractual delay fines.
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Ed Douglas
September 11, 2009
One Powerful Day: Live on September 29, 2009
Power Electronics Technology and the Electronic Design Group bring the latest in power design information direct to you, the design engineer, with our online conference ONE POWERFUL DAY. The conference brings you up to date on the latest in Power Design, and you can pick and choose the free sessions that benefit you the most.
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ED News Staff
August 19, 2009
CUI Joins PMBus Forum CUI Inc. is now a member of the Power Management Bus (PMBus) Implementers Forum. PMBus is an industry standard developed to allow power converters to communicate over a digital bus.
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ED News Staff
August 18, 2009
Cambridge and Armour Offer Internet Radio With The Q2 Cube
Marvell has released its Qdeo HD video evaluation Blu-ray disk. This disk performs an objective evaluation of the video processing quality of HD audio-video products such as Blu-ray players, AV receivers, and HDTVs. The disk tests video processing elements like noise reduction, format conversion, and image enhancement.
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ED News Staff
August 18, 2009
Marvell Introduces The Qdeo Disk For HD Video Evaluation
Marvell has released its Qdeo HD video evaluation Blu-ray disk. This disk performs an objective evaluation of the video processing quality of HD audio-video products such as Blu-ray players, AV receivers, and HDTVs. The disk tests video processing elements like noise reduction, format conversion, and image enhancement.
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ED News Staff
August 4, 2009
Entrepreneurial “Ecosystem” Launches For High-Tech
VentureOnLine is now in business. Launched by Amnon Aliphas, founder of TechOnLine, this gateway brings together entrepreneurs, investors, technology and business experts, project managers, and educational institutions in an effort to network and build business in the high-technology arena.
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ED News Staff
July 28, 2009
Keithley Series 2600A Source Meter Instruments
This video is a demonstration of Keithley's Series 2600A Source Meter instruments. After a brief introduction, the presenter shows how quickly and easily users can get results in lab and benchtop applications using the built-in TSP Express software tool.
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ED News Staff
June 2, 2009
Semiconductor Capacitance-Voltage (C-V) Testing Fundamentals
This seminar is designed to introduce the topic of C-V measurements as they relate to semiconductor device and materials characterization. C-V testing is commonly used to determine semiconductor parameters such as doping profiles, density of interface states, threshold voltages, oxide charge, and carrier lifetime.
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ED News Staff
May 18, 2009
Holding Out For Windows 7: A Wise Move?
While most businesses have soundly rejected Microsoft’s Windows Vista operating system and are tenaciously hanging on to Windows XP until the company comes out with a better OS, the day of reckoning approaches. The reason: Microsoft drove another stake into XP’s heart in April when it officially ended “mainstream support” for the OS.
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Joe Dysart
May 13, 2009
WI-FI 101
Wi-Fi (wireless fidelity) is one of the most widely used non-cellular wireless technologies. Wi-Fi is the trade name for products and systems that use the IEEE’s 802.11 standards for wireless local area networks (WLAN).
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Louis E. Frenzel
April 30, 2009
PCI eXtensions for Instrumentation (PXI) 101
PCI eXtensions for Instrumentation (PXI) is a rugged PC-based platform that offers a high-performance, low-cost means of deploying measurement and automation systems.
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David Maliniak
April 28, 2009
Timing Jitter 101
In any system that uses voltage transitions to represent timing information, jitter is an unfortunate part of the equation. In essence, jitter is the deviation of timing edges from their intended locations.
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David Maliniak
April 27, 2009
Intelligent Testbench 101
Functional verification of large SoC/ASIC designs has always been a catch-22 situation. How does the verification engineer decide that enough simulations have been run on a functional block or full chip? When has he or she thrown enough test vectors at the design to be confident that sufficient coverage has been achieved?
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David Maliniak
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