1135 results found for Web Exclusive, displaying items 1 - 20
September 8, 2008
Cadence Comes At Power From Two Perspectives
With a two-pronged approach, Cadence is attempting to enable designers to close the loop on low-power design. At the system level, an enhancement of the InCyte tool acquired through Chip Estimate results in greatly improved chip-level architectural power estimation. Meanwhile, an expansion of the Palladium emulation system provides for dynamic power analysis and cycle-accurate power estimation that is linked to accurate technology libraries and the synthesis flow.
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ED News Staff
September 2, 2008
Collaboration Results In First IEEE 1149.7 cJTAG Semiconductor IP Core
The industry’s first synthesizable IP core that implements the upcoming IEEE 1149.7 cJTAG standard, which will be ratified in early 2009, is available from IPextreme. The IEEE 1149.7 standard will provide designers with powerful extensions to the current IEEE 1149.1 (JTAG) standard, using fewer pins and maintaining compatibility...
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ED News Staff
September 2, 2008
Engineering A Hall Of Famer
Once a year we at Electronic Design ask our readers to stand up and recognize those who have made major contributions to the electronic engineering world. Our “2008 Electronic Design Hall of Fame” is primed to hoist another class of engineer superheroes onto your proverbial shoulders.
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John Arkontaky
August 29, 2008
Yield Enhancement Software To Aid Solar Cell Fabs
Magma Design Automation Inc. is developing a yield enhancement software system customized for solar fabs to improve conversion efficiency, increase yield and reduce the manufacturing costs of solar cells. Magma is collaborating with Pegasus Semiconductor-Solar to refine product specifications and test the new product, based on Magma’s YieldManager software system.
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ED News Staff
August 29, 2008
Audio Engine Codec Library Expands With Dolby Pro Logic Additions
Tensilica’s audio codec library for its Xtensa HiFi 2 Audio Engine has been expanded to include Dolby Pro Logic II and Pro Logic IIx decoders. Both Dolby Pro Logic decoders are essential sound processing technologies employed in home-theater AV receivers. Dolby Pro Logic II creates 5.1-channel surround sound from any stereo movie, music, TV, or game audio source, while Dolby Pro Logic IIx extends the sound experience up to a full 7.1-channel configuration.
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ED News Staff
August 29, 2008
Accellera Rolls New Version of Analog, Mixed-Signal Standard
Accellera’s Board of Directors and Technical Committee members have approved a new version of its Verilog-Analog Mixed-Signal (AMS) standard, Verilog-AMS 2.3, as an Accellera standard for analog and mixed-signal design and simulation. The new Verilog-AMS standard unifies the Verilog-AMS 2.2 specification with the IEEE Std. 1364-2005 or Verilog hardware description language (HDL) standard.
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ED News Staff
August 19, 2008
DNA In Your Gadgets?
We all know how DNA technology has revolutionized forensics as the unique identifier for organic life. Now here comes DNA technology for automobiles, motorcycles, marine equipment, clothing, laptops, building materials, packaging, industrial goods, construction equipment, etc.
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Roger Allan
August 18, 2008
User Advisory Group To Guide Open Verification Methodology’s Evolution
The best cooperative efforts in the EDA industry are guided by the collective input of users and technology providers. Those that aren’t tend to be dominated by one or two key players, making them somewhat less than truly cooperative. The Open Verification Methodology (OVM) World community is striving for the former path through its establishment of the OVM Advisory Group (OAG), an organization of distinguished users and ecosystem suppliers.
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ED News Staff
August 18, 2008
DDR3 and DDR2 Memory IP Bolsters SoC Designs
A full range of DesignWare DDR intellectual property (IP) is available for systems-on-a-chip (SoCs) that require an interface to high-performance DDR3, DDR2, and DDR memory subsystems. The DesignWare DDR IP delivers memory system performance of up to 1600 Mbps, which is the maximum data rate of the JEDEC DDR3 specification. The IP includes configurable protocol and memory controllers, integrated mixed-signal PHYs including I/Os, and verification IP.
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ED News Staff
August 18, 2008
PCB Tools Cross-Probe Between Layout And Schematic
Providing a valuable mechanism for design, review, verification, and testing of printed-circuit board (PCB) designs, CircuitSpace Foundation from DesignAdvance Systems now offers cross-probing between layouts and PDF schematics. The new cross-probing capability adds to CircuitSpace’s existing auto-clustering and replication technologies and works seamlessly within Cadence’s Allegro PCB design environment.
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ED News Staff
August 18, 2008
Constraint-Driven Flow Targets PCB High-Density Interconnects
With pin pitches shrinking on FPGAs and other IC packages, many printed-circuit board (PCB) designers—like it or not—are forced to enter the realm of high-density interconnects (HDIs). In response to this trend, Cadence has announced the SPB 16.2 release of its Allegro and OrCAD families of PCB design flow. While the flow has offered constraint-driven design for some time, that capability is now coupled with new features aimed at HDIs.
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ED News Staff
August 18, 2008
Cadence Abandons Its Bid To Buy Mentor Graphics
There will be no merger of Cadence Design Systems and Mentor Graphics after all. Cadence has withdrawn its proposal to acquire all of the outstanding shares of Mentor Graphics’ common stock. Instead, Cadence’s board of directors has authorized a $500 million increase to Cadence’s stock repurchase program.
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ED News Staff
August 15, 2008
Consumer Electronics Growth Tied To Better Design Coordination With Chip Suppliers
When it comes to designing new products, the consumer electronics (CE) and semiconductor sectors of the industry are going to have to get their acts together—literally, according to a joint study by the Consumer Electronics Association, the Global Semiconductor Alliance, and KPMG LLP, an audit, tax, and advisory firm. The study notes that CE producers are designing and developing their products much faster than IC suppliers can design the chips that drive them.
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Ron Schneiderman
August 14, 2008
A Summary Of The DDR Memory Controller Standard—Wait, There Isn’t One!
The number of SoCs that require an interface to off-chip memory is increasing. As a result, more and more designers are turning to DDR SDRAM interfaces such as DDR, DDR2, and DDR3 to address their low-cost, security of supply, storage capacity, and performance requirements. Fortunately for those designers, DRAMs have been standardized since the 1970s. But this still leaves a challenge that most SoC engineers don’t recognize until things start to go wrong.
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Graham Allan
August 14, 2008
Barbers, Adaptability, And Electric Pickup Trucks
A recent CNN story called “Converting Gas-Powered Cars to Electric” sparked a round of e-mails among us Electronic Design editors. The story specifically described a man who ripped the engine out of his Chevy S-10 pickup and installed an electric motor, reminding me of a conversation I had yesterday with Dave, my barber. Dave drives this brobdinagian pickup camper, and we were talking about what’s under its hood.
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Don Tuite
August 13, 2008
NIWeek Wrap Up
One of the best conferences I go to each year is NIWeek. Another has come and gone, but like always I got a glimpse at some solid technology from the mega-company. National Instruments has been sponsoring their own conference here in Austin, TX for several years now, and it has become a solid industry event. Why? Simply because NI’s products like LabVIEW software, data acquisition hardware, and virtual instruments have become so widely used.
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Louis E. Frenzel
August 12, 2008
Is It Worth Waiting For The Next Generation iPhone?
The media is simply overflowing with articles on Apple’s iPhone 2.0 which came out last month. (June 9). I have already had the feeling that I was the only writer/editor/blogger/pundit who had NOT written about this device. So, here is my two cents worth. But to liven this up, I will tell you what I think will be the new and better features of the third version of the iPhone, not the newest one, but the (hypothetical) one just beyond.
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Louis E. Frenzel
August 6, 2008
Solar Cars Cross The Continent
Hybrids and electric cars may get all the buzz these days, but what if you could leave the grid entirely? That may not be as far-fetched as you think, based on the results of the 2008 North American Solar Challenge. Last month, 15 teams and their sun-powered cars charged 2400 miles across the continent to test the technology’s viability.
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Richard Gawel
August 4, 2008
FPGA Tools Aid Power Reduction And Simplify Design Creation
The latest revision of Actel’s Libero Integrated Development Environment (IDE) gives designers additional power supply options and enables even lower power consumption. Libero IDE 8.4 offers an FPGA core operating-voltage range from 1.14 to 1.575 V for Actel’s flash-based Igloo, Igloo Plus and ProASIC3L FPGAs. Enhancements to the SmartPower analysis tools within the Libero IBE also ease comparisons of multiple design scenarios and their resulting power consumption and battery life implications.
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Staff
August 4, 2008
Enhancements Bolster RF Board Design Suite
With improvements to the reliability of artwork masks for electromagnetic (EM) verification and RF board manufacturing, the 2008.07 release of Agilent Technologies’ Genesys suite for RF printed-circuit board (PCB) design delivers shorter design cycles with less iteration for RF designers. The update also includes modeling and user-interface enhancements.
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Staff
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