Understanding Power Integrity as a System-Wide Challenge

By Matt Elmore, April 23, 2012

Power flows from boards to packages to chips; along the way are any number of impediments to power integrity. This article explains how to examine power integrity from a system-level perspective.

Verification IP Arrives For 12-Gbit/s SAS And NVM Express Protocols

By David Maliniak, April 23, 2012

With cloud computing all the rage, Cadence's verification IP is primed for functional verification of systems based on the 12-Gbit/s SAS and NVM Express protocols.

Audio IP Subsystem Configured For SoCs

By Paul Whytock, April 19, 2012

Synopsys claims it has developed the industry’s first complete audio IP subsystem. Called DesignWare SoundWave Audio Subsystem, it’s an integrated hardware and software audio IP subsystem for system-on-a-chip (SoC) designs.

Kit Generates Virtual Platforms With Power Debugging Support

By Bill Wong, April 14, 2012

Syynopsis' Virtualizer Development Kit (VDK) generates Arm architecture virtual prototypes suchas quad core Cortex-A15s or big.LITTLE platforms. It generates targets for software developers.

What’s The Difference Between Pre-Layout And Post-Layout PCB Simulation?

By Patrick Carrier, March 26, 2012

Simulation of a printed-circuit board design after placement and routing is good, but simulation beforehand is better. Mentor Graphics' Patrick Carrier explains just what can be done in simulation before board layout and what it buys you downstream.

Don’t Underestimate The Value of Standards

By Karen Bartleson, March 22, 2012

In her debut column, Karen Bartleson recaps why standards matter to design engineers and how they serve as a foundation for technology and business. Along the way, she gives shout-outs to some successful standards as well as a few failures.

Fundamentals Of Floor Planning A Complex SoC

By Andre Hassan, March 22, 2012

Many considerations go into the process of floor planning SoCs. Kilopass Technologies' Andre Hassan covers the basics in this tutorial.

Know Your Mandatory And Recommended 20-nm Tapeout Requirements

By Michael White, March 21, 2012

The move to the 20-nm process node presents challenges for tapeout, but they're not insurmountable. Mentor Graphics' Michael White cuts through the EDA marketing hype and takes a pragmatic look at what 20 nm means in terms of tool flows and verification.

What’s The Difference Between CTS, Multisource CTS, And Clock Mesh?

By Harvey Toyama, March 15, 2012

Multisource clock-tree synthesis is a relatively new option for clock distribution, joining conventional clock-tree synthesis and clock mesh. This article contrasts and compares these methods, examining the tradeoffs between them.

What’s The Difference Between Software Development Platforms?

By Frank Schirrmeister , March 15, 2012

Software development can involve virtual prototypes, RTL simulation, acceleration/emulation systems, and FPGA-based prototyping. This article breaks down when each is appropriate during the design cycle and explains their use cases.

What’s New in Eagle V6 PCB Design Software? Prepare for More Third-Party Tools

By Natasha Baker, March 14, 2012

Eagle v6 was recently released by CadSoft. This article covers what's new with this popular PCB design software as well as some of its drawbacks.

Virtual Platform Streamlines Software Development

By Staff, February 29, 2012

Design System Suits Automotive Apps

By Staff, February 29, 2012

IP Models Need To Work Everywhere

By Lauro Rizzatti, February 23, 2012

Without IP reuse, today's consumer products would be impossible. But IP vendors are complicating things with "black-box" models that don't run on all verification environments. EVE's Lauro Rizzatti proposes a solution.

Understanding Cell-Aware ATPG And User-Defined Fault Models

By Ron Press, February 23, 2012

ATPG targets faults at IC-gate boundaries, but 50% of defects are located within cells. Learn how cell-aware ATPG and user-defined fault models help to ferret out these hard-to-squash bugs.