NIOS II CORE CONFIGURATION OPTIONS
	Nios II/f	Nios II/s	Nios II/e
Stratix II	200 DMIPS at 175 MHz 1180 LEs 1 of 8 DSPs 4k L cache, 2k D cache Stratix 2S10-C5	90 DMIPS at 175 MHz 800 LEs 4k L cache, no D cache Stratix 2S10-C5	28 DMIPS at 190 MHz 400 LEs No L cache, no D cache Stratix 2S10-C5
Stratix	150 DMIPS at 135 MHz 1800 LEs 1 of 8 DSPs 4k L cache, 2k D cache Stratix 1S10-C5	67 DMIPS at 135 MHz 1200 LEs 4k L cache, no D cache Stratix 1S10-C5	22 DMIPS at 150 MHz 550 LEs No L cache, no D cache Stratix 1S10-C5
Cyclone	100 DMIPS at 125 MHz 1800 LEs 4k L cache, 1k D cache Cyclone 1C4-C6	62 DMIPS at 125 MHz 1200 LEs 2k L cache, no D cache Cyclone 1C4-C6	20 DMIPS at 140 MHz 550 LEs No L cache, No D cache Cyclone 1C4-C6
	FMax numbers-based reference design running from on-chip memory (Nios II/f =@1.15 DMIPS/MHz)