1512 results found for Electronic Design Automation, displaying items 1 - 20
June 25, 2009
[TechView: EDA] Accellera-SPIRIT Consortium Merger Boosts EDA Standards Efforts
Hoping to prove that two isn’t necessarily better than one, the EDA standards bodies Accellera and the SPIRIT Consortium have agreed to combine into a single organization. The combined entity, which will go forward as Accellera (with IP standards branded as SPIRIT IP-XACT), will seek to exploit synergies, and possible new opportunities, in the development of design and verification language-based and IP standards.
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David Maliniak
June 25, 2009[Leapfrog: First Look] Tool Automates Power Optimization Of Embedded SoC Memories
System-on-a-chip (SoC) design teams have long labored to optimize their creations for power, but doing so in the memory portions of the devices has lagged behind. Today’s memory-IP (intellectual property) providers build complex power-management schemes into their products, yet the design of the control logic to take maximum advantage of these schemes is daunting. Attempts to get a handle on dynamic power consumption using sleep modes are...
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David Maliniak
June 18, 2009[Technology Report] EDA Remains The Enabler Of Much-Needed Innovation
Some years ago, the electronic design Automation consortium (edAc) adopted the phrase â??where electronics Beginsâ?? as a tagline. coined by richard Goering during his EE Times days, the phrase remains more than apt for edA. As silicon integration grew more complex over the past three decades, the automation of otherwise manual and labor-intensive phases of the design cycle became ever more critical. one could scarcely imagine todayâ??s ...
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David Maliniak
June 11, 2009[TechView: EDA] Software Confronts New Yield-Management Paradigm
Yield analysis, a science formerly left to process engineers in foundries, is not a luxury any longer. According to Collett International’s research, at least 40% of designs face at least one respin with an associated delay of from four to six weeks. At least 22% of designs will see two respins, so make that delay 12 to 16 weeks. Some 60% of the issues causing these respins are silicon related. Let’s not forget that the new mask sets for each respin...
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David Maliniak
June 11, 2009[Engineering Feature] The Mixed-Signal Angle On DFM
When most designers think of DFM, they think of deep-submicron SoCs and digital design. But more often, DFM is a factor in analog/mixed-signal flows for RFICs as well. “There’s no such thing as a pure RFIC anymore,” says Marc Peterson, director of RFIC product planning at Agilent EEsof. “All RFICs are mixed-signal chips these days, and they’re moving to the smaller process nodes where process variability is a much bigger problem.” A key part of mixed-signal...
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David Maliniak
June 11, 2009[Engineering Feature] Design For Manufacturing Sheds The Hype
Four to five years ago, the hype surrounding design-for-manufacturing (DFM) technology for advanced system-on-a-chip (SoC) design was near insufferable. At that time, 90 nm was the state-ofthe- art process node and most fabless houses were preparing for a shrink down from the 130-nm node. And without some way of feeding process parameters back into the design side, the likelihood of any chip yielding at 90 nm was slim to none. This set off a bit of panic among the...
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David Maliniak
May 28, 2009
[From Systems to Silicon] Virtualization Innovations Drive Cost Optimization
The 2007 edition of the International Technology Roadmap for Semiconductors (ITRS) states that “design cost is the greatest threat to the continuation of the semiconductor roadmap.” While this claim has been made even long before then, in light of the current economic situation, its meaning could not be more relevant. Given that the semiconductor industry has been through economic cycles before, however, the ITRS is also able to suggest a remedy. It’s called innovation!
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Frank Schirrmeister
May 15, 2009
[From Systems to Silicon] When One Plus One Has To Be Less Than One
A customer recently suggested he could only add new steps to his process if the sum of the current workload and the additional workload to add the steps would result in less work overall. It took a little while for me to let that math settle in, but in retrospect this comment precisely explains one of the key issues preventing mainstream adoption of system-level design. ROI for system-level design is not quantifiable “enough,” which often deters metric-driven verification teams.
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Frank Schirrmeister
May 5, 2009
[Design View / Design Solution] Design Abstraction—A Practical View
The concept of applying a higher level of design abstraction to creative and engineering processes is so closely familiar that we probably take it for granted. From NC machines to SQL database systems, a high-level approach to capturing the design or operational intent of a system is universally accepted as the way it’s done.
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Rob Evans
April 28, 2009
[Design View / Design Solution] TLM-2.0 APIs Open SystemC To Mainstream Virtual Platform Adoption
At the 45th Design Automation Conference in June 2008, the Open SystemC Initiative (OSCI) announced the ratification of the TLM-2.0 standard, enabling interoperability for transaction-level models (TLMs). The next steps after ratification were to formalize a TLM-2.0 language reference manual (LRM) and eventually contribute the LRM to IEEE for further standardization once complete.
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Frank Schirrmeister
April 27, 2009
[Web Exclusive] Intelligent Testbench 101
Functional verification of large SoC/ASIC designs has always been a catch-22 situation. How does the verification engineer decide that enough simulations have been run on a functional block or full chip? When has he or she thrown enough test vectors at the design to be confident that sufficient coverage has been achieved?
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David Maliniak
April 23, 2009[Technology Report] Wireless-Enabled Systems Challenge Analog/Mixed-Signal Flows
FFrom its inception, the holy grail for the design automation industry has been in the analog realm. Digital logic, with its relatively straightforward structures and topologies, has long been the chief beneficiary of the EDA industry’s efforts. Yet compared to the digital domain, automation of analog and mixed-signal design remains lacking. There are some obvious factors at work. Chief among them is the painstakingly hands-on, custom nature of analog design work. ...
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David Maliniak
April 23, 2009[Technology Report] The MEMS Wrinkle
One RFIC maker with an interesting set of EDA challenges is WiSpry, which relies on RF-MEMS (microelectromechanical systems) technology to create its chips, components, and modules. The issues a design house faces in incorporating MEMS technology is one that more companies will face as MEMS make their way into a growing array of consumer electronics. There would be no Nintendo Wii game system without them. “We have the classic problem of having two separate tool chains to...
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David Maliniak
April 20, 2009
[TechView: EDA] IC Development Platform Integrates Proven Tools, Best Practices
Who’s got time to cobble together design flows from various vendors? Synopsys now offers the Lynx all-inclusive design system. And if the notion of procuring a design flow from a single vendor appeals, the Lynx Design System has some compelling points in its favor. At the heart of the Lynx Design System is Synopsys’ production design flow, which rests on a foundation of best practices and recommended methodologies for the best ways to drive tools such as Design Compiler.
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David Maliniak
March 26, 2009
[TechView: EDA] Try Easing Into Adoption of Formal Verification
Adopters of formal verification have reaped benefits from their efforts. Those who have taken the plunge report that assertion-based verification translates into gains in productivity and quality. But formal verification requires quite a bit of know-how to really take advantage of it. The lack of that know-how has stymied a lot of would-be adopters over the years. To ease the path, OneSpin Solutions has come up with a step-by-step approach to comprehensive assertion-based formal verification.
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David Maliniak
March 24, 2009
[Technology In The News] Winners Of Live EDGE To Be Announced
Service distributor Premier Farnell plc and its companies Farnell, Newark, Premier Electronics, Farnell-Newark CPC, and MCM will announce the winners for the Live Electronic Design for the Global Environment (EDGE) during a special virtual communications technology conference on April 2.
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ED News Staff
March 11, 2009
[From Systems to Silicon] Is System-Level Design About Discipline?
We’ve all heard it, and it’s said in many ways. Preparation is everything! System-level design is all about thinking early and implementing later. So why not apply what we already know? We even have statistics. Everybody seems to know and agree that it becomes more difficult to find and fix defects the further a project has progressed.
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Frank Schirrmeister
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