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Electronic Design Automation
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1341 results found for Electronic Design Automation, displaying items 1 - 20 |
May 8, 2008
[Technology In The News]
Accellera Works On Interoperable Verification Standards
Accellera, the electronics industry organization focused on EDA standards, has formed a verification standards committee to define standard technology and/or methods to realize a modular, scalable, and reusable generic verification environment. The goal of the Verification Intellectual Property (VIP) Technical Subcommittee is to reduce verification costs and improve design quality.
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ED News Staff
May 6, 2008
[Designed In]
TriQuint Supplying MMICs For Army Phased-Array Radar
TriQuint Semiconductor has started shipping production GaAs monolithic microwave ICs to Lockheed Martin Radar Systems for use in the EQ-36 Counterfire Target Acquisition Radars being developed for the U.S. Army. The new devices are the latest products to be developed for Lockheed Martin in a relationship that has also included work on radar programs for ship-borne and aircraft systems.
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ED News Staff
May 8, 2008
[TechView: EDA]
Try-Before-You-Buy IP Distribution Program Segues Into Implementation
As FPGAs become an increasingly popular implementation platform, their complexity rises accordingly, thanks largely to the proliferation of processor and peripheral IP. A study done by Synplicity last fall found that one-third of all designs implemented on FPGA these days carries at least some IP. With so many designers implementing IP on FPGAs, it would be useful if they had a vehicle through which they can acquire, evaluate, and...
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David Maliniak
May 5, 2008
[Web Exclusive]
3D EM-Field Simulator Goes Through Upgrade
Version 11.1 of Ansoft’s HFSS software for 3D full-wave electromagnetic field simulation is now available, offering a number of new enhancements. The tool now offers meshing as well as model resolution and validation features. It supports Nastran (.nas) geometry import as well as Parasolid and Unigraphic geometry import (the latter under Windows only). It also offers enhanced post-processing features.
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Staff
May 5, 2008
[Web Exclusive]
Enhancements Perk Up Spice Tool Suite
The latest release of Intusoft’s ICAP/4 Spice-simulation suite includes enhancements in waveform-creation capabilities as well as in automated component conversions. Build 3247 of ICAP/4 8.x.11 is also reported as having had the fewest bugs in Intusoft’s history during the company’s testing cycle on the revision.
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Staff
May 5, 2008
[Web Exclusive]
SoC/ASIC Verification System Is Fast And Scalable
Targeting SoC/ASIC developers of projects from 3 Mgates to 180 Mgates, the latest generation of GiDEL’s PROC_SoC Verification System doubles the capacity offered by previous versions by incorporating Altera’s Stratix III EP3SL40 FPGAs.
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Staff
May 5, 2008
[Web Exclusive]
Tool Ferrets Out Analog/RF Circuit Noise
Device noise is insidious to gigahertz, nanometer-scale analog, and RF CMOS circuit performance. In the past, it’s been either impractical or outright impossible to perform transistor-level analysis of the impact of device noise for many complex analog and RF circuits including sigma-delta ADCs, video DACs, fractional-N PLLs, frequency synthesizers, and wideband VCOs.
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Staff
April 24, 2008
[Electronic Design TOC Newsletter]
April 24, 2008
Radio Interoperability—It's Harder Than It Looks
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Staff
April 24, 2008
[Technology Report]
Multicore Design Benefits From Virtual Prototyping
Debugging system issues has always been a difficult task. Unfortunately, as multicore systems become more prevalent, debugging becomes substantially more difficult. The programmer must now deal with all of the previous issues, plus the resource contention and deadlock problems inherent in most multicore designs. Many times, these problems are impossible to debug by simply looking at registers through a JTAG connection. Needless to say, a better solution is required. Virtual...
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Bill Neifert
April 24, 2008
[Technology Report]
Programming Multicore Platforms: What’s Really Going On?
The reusable hardware platform, bristling with a range of processor architectures, is becoming commonplace. But even as processor vendors tout their latest multicore offerings, the effective programming of these complex devices remains an open question. Academia will rise to the challenge with expansive programming models and methodologies in the future. In the meantime, the widening programmability gap threatens to choke design productivity. Let’s examine the brave new multicore...
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David Stewart
April 24, 2008
[Technology Report]
Software Rules The Day In Multicore SoC Design
Looking back over the past 10 years or so, semiconductor process technology more or less kept pace with the demand for functionality in large-scale processor-based ICs. When the next-generation set-topbox IC needed more horsepower, a move from, say, a 180-nm process to 130 nm would provide the necessary boost by adding gates and the ability to run faster clocks. But that next-gen chip would still carry a single processor. Things have changed dramatically...
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David Maliniak
April 24, 2008
[TechView: EDA]
Design Flow Halves Development Time For Mixed-Technology PCBs
Once found chiefly in the military and aerospace domains, printed-circuit boards (PCBs) with a mélange of analog, digital, and RF circuitry are now everywhere. In fact, the wireless telecom and consumer sectors are embracing them wholeheartedly. But that doesn’t mean they’ve gotten any easier to design. Mixed-technology PCBs are only growing in density and complexity, encompassing more layers than ever, multiple power domains, and greater sensitivity...
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David Maliniak
April 16, 2008
[Electronic Design UPDATE]
Electronic Design Update: April 16, 2008
Fibre Channel (FC) has been the storage-area network (SAN) connection technology of choice for years. Competition from the Ethernet-based iSCSI has made SAN market inroads over the past few years, and there’s no doubt that increased competition will continue. However, FC certainly isn’t dead.
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John Arkontaky
, et al.
April 15, 2008
[Web Exclusive]
European Research Yields COCONUT Fruit
A European research project coordinated by the University of Verona, Italy, hopes to define a formal framework based on tight integration of design and verification through all the refinement steps of an embedded-platform design flow. The project, which spans specification through logic synthesis and software compilation, also aims to propose a modeling and verification flow that enhances and speeds up embedded platform design and configuration.
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Staff
April 15, 2008
[EDA Alert]
EDA Alert: April 15, 2008
"You say you want a revolution? Well, you know . . . we all want to change the world."
John Lennon penned that opening line of The Beatles' "Revolution" in 1968. And it's just as relevant now as it was 40 years ago. The electronics industry stands on the threshold of an era of creative innovation as it rushes toward multicore system-on-a-chip (SoC) design.
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David Maliniak
April 14, 2008
[Web Exclusive]
You Say You Want a Revolution, You’ll Find One In OVP
“You say you want a revolution? Well, you know . . . we all want to change the world.”
John Lennon penned that opening line of The Beatles’ “Revolution” in 1968. And it’s just as relevant now as it was 40 years ago. The electronics industry stands on the threshold of an era of creative innovation as it rushes toward multicore system-on-a-chip (SoC) design.
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Simon Davidmann
April 14, 2008
[Web Exclusive]
Hardware-Accelerated Spice Simulator Raises Speed/Accuracy Bar
Nascentric’s OmegaSim GX is touted as the world’s first hardware-accelerated Spice simulator. OmegaSim GX harnesses the raw computational power of NVIDIA Graphics Processing Units (GPUs) to provide fast transistor-level simulation with virtually no loss in accuracy.
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Staff
April 14, 2008
[Web Exclusive]
Pyxis Technology, Silicon Canvas Set Interoperability Milestone
The dream of true EDA-tool interoperability—meaning simultaneous execution of two commercial tools within the same Unix process—has long eluded tool users, unless, of course, you’re talking about tools integrated as a proprietary combination from the same vendor.
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Staff
April 14, 2008
[Web Exclusive]
Modeling Extensions Help Verify Datapath Designs
A set of four modeling extensions to Jasper Design Automation’s Proof Accelerators provides for fast—and exhaustive—verification of intractable datapath designs. Jasper’s JasperGold Proof Accelerators can be used to speed the functional verification of any complex chip design in which datapath, multiple clock domains, caches, and FIFOs pose challenges.
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Staff
April 10, 2008
[Electronic Design TOC Newsletter]
April 10, 2008
Portable Media Keeps Playing And Playing And...
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Staff
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