1527 results found for Electronic Design Automation, displaying items 1 - 20
November 5, 2009[TechView: EDA] Parasitic Extraction Tool Targets Next-Generation Custom ICs
Achieving design closure in a system-on-a-chip (SoC) development project generally requires a great deal of patience. SoCs tend to include more and more custom circuitry, which means long simulation runs and some stabs in the dark at something resembling signoff. The combination of more transistors and the need to model more complex parasitic effects can double, if not quadruple, the runtimes of circuit-level simulation. One way to get...
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David Maliniak
October 29, 2009
[TechView: EDA] Synopsys Jumps Into ESL-Synthesis Pool
There’s a new entry in the ESL synthesis marketplace in the form of the Synopsys Synphony high-level synthesis (HLS) tool, which the company has aimed directly at the heart of the burgeoning HLS market. Synphony is intended to synthesize algorithms written in the MathWorks’ Matlab language into optimized RTL for ASICs, FPGAs, prototyping, and software development work.
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David Maliniak
October 1, 2009[Engineering Essentials] Verify Control Systems Before Committing To Hardware
Embedded-control system designers feel more pressure than ever to provide better performance and more features, all while meeting tight deadlines and keeping costs down. As these demands intensify, traditional design and verification methodologies tend to fall short. In traditional design flows, designers can’t determine if their controller works until late in the effort, when hardware is available. This was often sufficient for ...
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Brian McKay
September 24, 2009[Technology Report] You're Using How Many FPGAs?
Designing a single-purpose FPGA prototype board is hard enough. But what about a register-transfer-level (RTL) emulation system based on FPGAs? Emulators are known for their fast compile times and simulator-like debug capabilities—features not normally associated with FPGAs. Throw in the need to support up to 1 billion ASIC-equivalent gates as well as multiple concurrent users with multiple use models, and you’ve got quite a challenge. That, in fact, is the challenge EVE faced while...
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Ron Choi
September 24, 2009[Technology Report] Tool Up For The FPGA Blitz
FPGA usage divides into two primary segments. Historically, the foremost role of FPGAs has been to verify an ASIC, system-on-achip (SoC), or application-specific standard part (ASSP). Designers now will use FPGAs to prototype a portion or all of their design, to tweak the same, or as a platform to get ahead on developing system software. According to some industry experts, as many as 90% to 100% of ASICs today are prototyped on FPGAs. For many years, a main...
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David Maliniak
September 10, 2009[Embedded in Electronic Design] Support Will Have Android Showing Up In Embedded Apps
Android has lots of buzz, especially when it comes to smart phones. But it also will be showing up in embedded applications as the range of support expands. One of the leaders is Mentor Graphics. Its recent acquisition of Embedded Alley, a major Android supporter, was highlighted at this year’s DAC 2009 show. Mentor Graphics is looking to support smart-phone developers as well as anyone else interested in utilizing Android in an embedded application....
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William Wong
August 25, 2009
[Lab Bench] New Power-Management Policies Emerge At DAC
Power management was high on the feature lists of the products shown at July’s Design Automation Conference in San Francisco. For example, Mentor Graphics highlighted new features in its Vista platform that allow users to model, analyze, and optimize power at the transaction level of abstraction. Synopsys showed off its DesignWare minPower Components, which are designed to provide major reductions in power for datapath logic compared to traditional power optimization methods.
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William Wong
August 12, 2009
[Lab Bench] Counting Down The Top 10 New Features In LabVIEW 2009
The latest version of National Instruments' LabVIEW includes a number of improvements. Key enhancements include its 3D Math Plots, Verification and Validation support, Partial Block Cleanup, Icon Editor, MathScriptRT Module, FPGA Compile Window, StatechartAutoDocs, VI Snippets, Real-Time Hypervisor, and LabVIEW versioning.
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William Wong
August 12, 2009
[Editorial] At NI Week, Innovation Always Takes Center Stage
Anyone who has attended NI Week comes to expect a certain level of innovation to be on display, based on products such as LabVIEW. NI Week is, of course, the annual pilgrimage of LabVIEW users to a three-day conference, hosted by National Instruments, that’s filled with education, motivation, excitement, and just plain fun. This year did not disappoint.
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Joseph Desposito
July 29, 2009
[From Systems to Silicon] Embedded Hardware And Software—Like Two Camps With A River Full Of Sharks In Between
At least for the last decade, we have been hearing about the worlds of embedded software and hardware growing closer, but there has been very little measurable evidence to back up those claims. Still, I’m cautiously optimistic that we are starting to see a shift toward true co-development of hardware and software, or at least its co-debug. My optimism is driven by the results of a couple of user surveys Synopsys conducted last year.
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Frank Schirrmeister
July 23, 2009[Leapfrog: First Look] In Adding Control-Logic Support, A High-Level Synthesis Tool Goes Full Chip
High-level synthesis (HLS), or the notion of synthesizing a design into RTL from a higher level of abstraction, has been gaining currency among design teams. For some time now, there have been compelling reasons to explore HLS methodologies for certain kinds of designs, or certain blocks within a larger design, such as signal- processing blocks. Such a design flow can get you to RTL faster from languages like C++ or SystemC. And because simulation at the transaction...
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David Maliniak
July 23, 2009[Design View / Design Solution] Formal Methodology Validates Cache-Coherence Protocol
Bugs in RTL code are problematic, but a bug in an architectural specification can be catastrophic. If the bug remains undetected until post-silicon debugging, the design process essentially starts all over again. Thus, it’s crucial to move the verification process as far forward as possible. With that motivation in mind, engineers at Sun Microsystems recently applied formal verification to an application that commercial tools have not generally...
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Norris Ip
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July 23, 2009[Technology Report] 46th DAC Is This July’s San Francisco Treat
Attendees of past Design Automation Conferences (DACs) could count on hearing from EDA vendors and design technologists. This year’s 46th DAC takes a significant step by adding the voices of the tool users themselves. With more than 80 papers focused on the latest in tool use and methodologies, the User Track joins DAC’s technical program when the conference kicks off July 26-31 at the Moscone Center in San Francisco. The 46th DAC’s technical program comprises...
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David Maliniak
June 25, 2009
[TechView: EDA] Accellera-SPIRIT Consortium Merger Boosts EDA Standards Efforts
Hoping to prove that two isn’t necessarily better than one, the EDA standards bodies Accellera and the SPIRIT Consortium have agreed to combine into a single organization. The combined entity, which will go forward as Accellera (with IP standards branded as SPIRIT IP-XACT), will seek to exploit synergies, and possible new opportunities, in the development of design and verification language-based and IP standards.
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David Maliniak
June 25, 2009[Leapfrog: First Look] Tool Automates Power Optimization Of Embedded SoC Memories
System-on-a-chip (SoC) design teams have long labored to optimize their creations for power, but doing so in the memory portions of the devices has lagged behind. Today’s memory-IP (intellectual property) providers build complex power-management schemes into their products, yet the design of the control logic to take maximum advantage of these schemes is daunting. Attempts to get a handle on dynamic power consumption using sleep modes are...
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David Maliniak
June 18, 2009[Technology Report] EDA Remains The Enabler Of Much-Needed Innovation
Some years ago, the electronic design Automation consortium (edAc) adopted the phrase â??where electronics Beginsâ?? as a tagline. coined by richard Goering during his EE Times days, the phrase remains more than apt for edA. As silicon integration grew more complex over the past three decades, the automation of otherwise manual and labor-intensive phases of the design cycle became ever more critical. one could scarcely imagine todayâ??s ...
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David Maliniak
June 11, 2009[TechView: EDA] Software Confronts New Yield-Management Paradigm
Yield analysis, a science formerly left to process engineers in foundries, is not a luxury any longer. According to Collett International’s research, at least 40% of designs face at least one respin with an associated delay of from four to six weeks. At least 22% of designs will see two respins, so make that delay 12 to 16 weeks. Some 60% of the issues causing these respins are silicon related. Let’s not forget that the new mask sets for each respin...
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David Maliniak
June 11, 2009[Engineering Feature] The Mixed-Signal Angle On DFM
When most designers think of DFM, they think of deep-submicron SoCs and digital design. But more often, DFM is a factor in analog/mixed-signal flows for RFICs as well. “There’s no such thing as a pure RFIC anymore,” says Marc Peterson, director of RFIC product planning at Agilent EEsof. “All RFICs are mixed-signal chips these days, and they’re moving to the smaller process nodes where process variability is a much bigger problem.” A key part of mixed-signal...
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David Maliniak
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