Advances in new devices confront packaging engineers with pressing demands for packages with smaller footprints, higher device speeds, and lower costs. These demands are driving the implementation of chip-scale packages (CSPs) for increasingly complex ADCs.
The fine-pitch ball-grid array (fpBGA) CSP is 60% to 80% smaller, at equivalent lead counts, than its predecessor, the BGA package. The 1.27-mm BGA solder ball pitch has shrunk to 1.0 mm and less for the fpBGA, even to 0.5 mm today, and 0.4 mm in the future. Analog Devices' leadframe CSP (LFCSP) is 60% to 85% smaller, at equivalent lead counts, than standard leadframe packages, as the leads don't extend outside the perimeter of the package body.
Both fpBGA and LFCSP packages achieve significantly reduced footprints while accommodating higher lead counts and increasingly complex, higher-speed devices. The smaller size and increased electrical performance are enabled by the tighter pitches of the I/O interconnects and the lower inductances that result from the shorter lead traces in the CSP. Quad high-speed ADCs with serial outputs, which couldn't be easily produced in older packages, use this CSP platform, and all at lower cost-per-lead than the displaced solutions. Still smaller solutions are enabled with bumped die CSP technology, ideal for assembly into modules and in stacked-die applications for cameras and cell-phones.