Not many off-the-shelf ADCs use continuous-time delta-sigma technology. So to get a clearer understanding of the technology, we'll compare it to discrete-time delta-sigma. The major difference between discrete and continuous sampling in a delta-sigma lies in the loop filter. Discrete sampling employs a switched-capacitor filter, which demands fast settling circuits and requires an input buffer to eliminate sample glitches.
A number of other disadvantages hinder switched-capacitor loop filters. For example, switched-capacitor input filters set their poles and zeroes through capacitor ratios relative to the sampling clock frequency. Because capacitor thermal noise is inversely proportional to capacitance, the capacitors must be relatively large to obtain the best signal-to-noise ratio.
Obviously, in discrete-time converters, switched-capacitor stages limit the maximum signal bandwidth. In contrast, continuous-time loop filters open up new application possibilities, including baseband sampling out to several tens of megahertz and undersampling RF signals in bandpass designs.
Also, to acquire an accurate representation of the input signal on a hold capacitor, the input stages must settle to a finite level dictated by the accuracy limits of the system. During acquisition, settling time depends on the exponential time constant and slew rate of the system.
Of course, switched-capacitor inputs aren't all bad. In discrete-time converters with switched-capacitor inputs, the good news is that the discrete-time input filter characteristic scales with clock frequency. Filter performance, therefore, always matches the sample clock rate. Still, the higher the clock frequency, the more the dynamic power consumed.
In contrast to discrete-time delta-sigmas, continuous-time sampling converters employ a high-order op-amp integrator filter, which is easier to drive because of the purely resistive nature of its input. Essentially, there's no acquisition phase, eliminating the need for a sample-and-hold stage. Nor does continuous-time require high gain-bandwidth stages to force rapid settling. Most significantly, for small process geometries that operate at low supply voltages, it supports ?beyond-the-rails? inputs.
The continuous-time delta-sigma equivalent input circuit is modeled by a resistor driving into a virtual ground. As a result, using this current-driven input stage won't limit the input voltage range to the extent of the converter's supply voltage range. For instance, Xignal's first product achieves a 4-V p-p input range despite operating from a single 1.2-V supply.
So what has held back the implementation of continuous-time conversion? Generally speaking, such converters aren't easy to design. For one thing, the filter characteristic is no longer tied to the filter sample clock. Instead, its performance depends on conventional active filter design rules. If the sample rate is changed to match input-signal bandwidth, the continuous-time filter must be tuned. It becomes a real challenge to ensure that a wide range of sample rates can be supported from a single product platform. Xignal deals with this by combining adaptive filter networks with calibration.
A further challenge lies in achieving high linearity in high-resolution implementations, because the loop filter requires plenty of gain. Xignal developed multi-path and cascaded gain stages that in 0.13-μm CMOS, operating at 1.2 V, nonetheless achieve 80-dB gain for a 30-MHz bandwidth. Thus, in its 14-bit chip, which has a theoretical 86-dB SNR, the current digital filter allows 90% of the available Nyquist bandwidth to be exploited while offering a passband ripple of ± 0.0002 dB, plus 80 dB of stop-band attenuation. Group delay for this filter is 0.33 samples.