Industrial controllers, programmable- logic controllers (PLCs), and data-acquisition systems often use 0- to 5-V, 0- to 10-V, ±5-V, ±10-V, and 4-to- 20-mA current loops to transmit the values of analog control signals. For safety reasons, some analog-output modules also employ optocouplers to electrically isolate the microprocessor and analog circuits. Also for safety, as well as reliability, other systems require that the analog outputs must reset to mid-scale or zero in response to a microprocessor failure.
Such requirements are met by this circuit (Fig. 1). It monitors microprocessor activity and sets the analog output to zero when it detects a microprocessor failure or an undervoltage condition. The device also improves the mean time between failures (MTBF) by minimizing I/O pin usage at the microprocessor and eliminating an optocoupler.
Three elements enable the DAC (U2) to produce zero-scale resets: an asynchronous- reset input ( −−CLR), a user-selectable reset-value input (RSTVAL), and a user-programmable output (UPO) for serial-interface setup. These built-in features also eliminate an optocoupler, reducing I/O pin usage at the microprocessor and the need for external discrete circuitry. The microprocessor supervisor (U1) includes a resistorprogrammable reset-input threshold, a capacitor-programmable watchdog timer, and a reset-timeout period.
As DAC codes range from 000H to FFFH, the circuit output (VOUT) ranges from -10 to 10 V. Op amp U1A is offset by the DAC’s internal, 10-ppm/°C precision bandgap reference. The output op amp, U1B, is configured as a buffer with a gain of four. The output voltage for the circuit is given by VOUT = VREF × (G × NB/4096 − 1) × (RF/RIN + 1). Here, NB is the numeric value of the DAC’s binary code, VREF is the internal reference voltage, G is the gain of U1A, and RF/RIN is U1B’s gain-resistor ratio.
U3 monitors the isolated supply voltage (VISO) via its VCC pin. It also monitors microprocessor activity using its WDI pin and generates a reset command by way of its RESET pin. A resistor divider at RESET IN (pin 1) determines the reset-level threshold (VTH). Similarly, the reset timeout period (tRP) and watchdog timeout period (tWD) are determined by capacitor values on the SRT and SWT pins of U3, respectively. Connecting WDS to VCC extends tRP by a factor of 500. The following equations calculate values needed in the circuit:
VRST = VTH (R1 + R2)/R2
CRST = tRP/2.67, where CRST is in pF
CSWT = tWD/2.67, where tWD is in µs
Here, VTH = 1.22 V and VRST is the adjustable reset-threshold voltage.
If VCC fails, or if the microprocessor locks up and cannot toggle the WDI input, U3 asserts a low on its −−RESET output, which resets U2 via its CLR input. This action resets U2’s output to the condition set by RSTVAL (to mid-scale in this case, which produces 0 V at VOUT).
When U2 is being updated, its UPO output toggles U3’s WDI input at intervals less than the nominal watchdog timeout (tWD = 25 seconds, subject to tolerances on the capacitor and the ICs).
Other devices that can be used for the watchdog function are the MAX6316 series and MAX6369 series. Both families offer fixed timeout periods in SOT23 packages. The switch between U3’s RESET IN and GND terminals allows the user to command an emergency shutdown. −−RESET pulls CLR high after the reset timeout (tRP ≈ 60 ms) but the DAC output remains at mid-scale until updated.
The DAC’s unipolar and bipolar modes allow it to produce all the common analog-output control signals.